From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A164C433F5 for ; Tue, 21 Sep 2021 16:23:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3403061107 for ; Tue, 21 Sep 2021 16:23:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3403061107 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Erm/+Rrp8hyOmDbNuGsjTAmEj3eY6JSsZNMKvO0Kbvk=; b=rBNc+QgLpvFeEuInsuUgtt1rY5 1siFu2fPA1ucv5bqi5VpfknCrJuinyOBc/aQ+wSFw4PW+RQSDFuaji63tWszNEdzOXj9yhMtPRKRQ 25ADsKoRgahRIybYs4K82jfRU0rkQTOyaph8jpzyvg0l/rXAofJ0BOctEC8X1POXl70hHOo4GZcJ8 1lU68WPS9OhfvWEJWki7mVrg1w5cjcnKNuiXFKjxVwb/S+NMUiGKvDk4eFmIryRkPtwNTkreVQ5bW +McbyfyMUvcrUob/V2fpbPt6ReQyfOf9qnF76nxpS9QXY7BFGlQ2a0kqpRonU6uwZYN7W5q4TUML+ greYc3nA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSiXR-005BiT-Tg; Tue, 21 Sep 2021 16:22:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSiXN-005Bgs-Mg for linux-arm-kernel@lists.infradead.org; Tue, 21 Sep 2021 16:22:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52BD4113E; Tue, 21 Sep 2021 09:22:26 -0700 (PDT) Received: from [10.57.95.67] (unknown [10.57.95.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34BBC3F718; Tue, 21 Sep 2021 09:22:25 -0700 (PDT) Subject: Re: [PATCH] coresight: Don't immediately close events that are run on invalid CPU/sink combos To: Mathieu Poirier , James Clark Cc: coresight@lists.linaro.org, Mike Leach , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210921130231.386095-1-james.clark@arm.com> <20210921151721.GA2059841@p14s> From: Suzuki K Poulose Message-ID: <2d1326ea-a60c-8723-28a4-891a5478846f@arm.com> Date: Tue, 21 Sep 2021 17:22:23 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20210921151721.GA2059841@p14s> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_092229_883467_794F6400 X-CRM114-Status: GOOD ( 28.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 21/09/2021 16:17, Mathieu Poirier wrote: > On Tue, Sep 21, 2021 at 02:02:31PM +0100, James Clark wrote: >> When a traced process runs on a CPU that can't reach the selected sink, >> the event will be stopped with PERF_HES_STOPPED. This means that even if >> the process migrates to a valid CPU, tracing will not resume. >> >> This can be reproduced (on N1SDP) by using taskset to start the process >> on CPU 0, and then switching it to CPU 2 (ETF 1 is only reachable from >> CPU 2): >> >> taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- taskset --cpu-list 2 ls >> >> This produces a single 0 length AUX record, and then no more trace: >> >> 0x3c8 [0x30]: PERF_RECORD_AUX offset: 0 size: 0 flags: 0x1 [T] >> >> After the fix, the same command produces normal AUX records. The perf >> self test "89: Check Arm CoreSight trace data recording and synthesized >> samples" no longer fails intermittently. This was because the taskset in >> the test is after the fork, so there is a period where the task is >> scheduled on a random CPU rather than forced to a valid one. >> >> Specifically selecting an invalid CPU will still result in a failure to >> open the event because it will never produce trace: >> >> ./perf record -C 2 -e cs_etm/@tmc_etf0/ >> failed to mmap with 12 (Cannot allocate memory) >> >> The only scenario that has changed is if the CPU mask has a valid CPU >> sink combo in it. >> >> Testing >> ======= >> >> * Coresight self test passes consistently: >> ./perf test Coresight >> >> * CPU wide mode still produces trace: >> ./perf record -e cs_etm// -a >> >> * Invalid -C options still fail to open: >> ./perf record -C 2,3 -e cs_etm/@tmc_etf0/ >> failed to mmap with 12 (Cannot allocate memory) >> >> * Migrating a task to a valid sink/CPU now produces trace: >> taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- taskset --cpu-list 2 ls >> >> * If the task remains on an invalid CPU, no trace is emitted: >> taskset --cpu-list 0 ./perf record -e cs_etm/@tmc_etf1/ --per-thread -- ls >> >> Signed-off-by: James Clark >> --- >> .../hwtracing/coresight/coresight-etm-perf.c | 27 +++++++++++++++---- >> 1 file changed, 22 insertions(+), 5 deletions(-) > > Very interesting corner case - and I like your solution. Arnaldo, please > consider. > > Reviewed-by: Mathieu Poirier > PS: This is for coresight driver, I can pick this up. Otherwise, Reviewed-by: Suzuki K Poulose >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c >> index 8ebd728d3a80..79346f0f0e0b 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >> @@ -452,9 +452,14 @@ static void etm_event_start(struct perf_event *event, int flags) >> * sink from this ETM. We can't do much in this case if >> * the sink was specified or hinted to the driver. For >> * now, simply don't record anything on this ETM. >> + * >> + * As such we pretend that everything is fine, and let >> + * it continue without actually tracing. The event could >> + * continue tracing when it moves to a CPU where it is >> + * reachable to a sink. >> */ >> if (!cpumask_test_cpu(cpu, &event_data->mask)) >> - goto fail_end_stop; >> + goto out; >> >> path = etm_event_cpu_path(event_data, cpu); >> /* We need a sink, no need to continue without one */ >> @@ -466,16 +471,15 @@ static void etm_event_start(struct perf_event *event, int flags) >> if (coresight_enable_path(path, CS_MODE_PERF, handle)) >> goto fail_end_stop; >> >> - /* Tell the perf core the event is alive */ >> - event->hw.state = 0; >> - >> /* Finally enable the tracer */ >> if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) >> goto fail_disable_path; >> >> +out: >> + /* Tell the perf core the event is alive */ >> + event->hw.state = 0; >> /* Save the event_data for this ETM */ >> ctxt->event_data = event_data; >> -out: >> return; >> >> fail_disable_path: >> @@ -517,6 +521,19 @@ static void etm_event_stop(struct perf_event *event, int mode) >> if (WARN_ON(!event_data)) >> return; >> >> + /* >> + * Check if this ETM was allowed to trace, as decided at >> + * etm_setup_aux(). If it wasn't allowed to trace, then >> + * nothing needs to be torn down other than outputting a >> + * zero sized record. >> + */ >> + if (handle->event && (mode & PERF_EF_UPDATE) && >> + !cpumask_test_cpu(cpu, &event_data->mask)) { >> + event->hw.state = PERF_HES_STOPPED; >> + perf_aux_output_end(handle, 0); >> + return; >> + } >> + >> if (!csdev) >> return; >> >> -- >> 2.28.0 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel