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[2003:d8:2f1e:2200:30f4:30:4011:370e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458953cfd10sm300498035e9.21.2025.08.06.01.19.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 01:19:04 -0700 (PDT) Message-ID: <2d213b5c-555e-4a4c-92bc-58ca8480ca64@redhat.com> Date: Wed, 6 Aug 2025 10:19:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 6/7] mm: Optimize mprotect() by PTE batching To: Will Deacon Cc: Dev Jain , akpm@linux-foundation.org, ryan.roberts@arm.com, willy@infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, Liam.Howlett@oracle.com, lorenzo.stoakes@oracle.com, vbabka@suse.cz, jannh@google.com, anshuman.khandual@arm.com, peterx@redhat.com, joey.gouly@arm.com, ioworker0@gmail.com, baohua@kernel.org, kevin.brodsky@arm.com, quic_zhenhuah@quicinc.com, christophe.leroy@csgroup.eu, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, hughd@google.com, yang@os.amperecomputing.com, ziy@nvidia.com References: <20250718090244.21092-1-dev.jain@arm.com> <20250718090244.21092-7-dev.jain@arm.com> <7567c594-7588-49e0-8b09-2a591181b24d@redhat.com> From: David Hildenbrand Autocrypt: addr=david@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250806_011909_097314_0CA7AAA4 X-CRM114-Status: GOOD ( 27.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 06.08.25 10:15, Will Deacon wrote: > On Wed, Aug 06, 2025 at 10:08:33AM +0200, David Hildenbrand wrote: >> On 18.07.25 11:02, Dev Jain wrote: >>> Use folio_pte_batch to batch process a large folio. Note that, PTE >>> batching here will save a few function calls, and this strategy in certain >>> cases (not this one) batches atomic operations in general, so we have >>> a performance win for all arches. This patch paves the way for patch 7 >>> which will help us elide the TLBI per contig block on arm64. >>> >>> The correctness of this patch lies on the correctness of setting the >>> new ptes based upon information only from the first pte of the batch >>> (which may also have accumulated a/d bits via modify_prot_start_ptes()). >>> >>> Observe that the flag combination we pass to mprotect_folio_pte_batch() >>> guarantees that the batch is uniform w.r.t the soft-dirty bit and the >>> writable bit. Therefore, the only bits which may differ are the a/d bits. >>> So we only need to worry about code which is concerned about the a/d bits >>> of the PTEs. >>> >>> Setting extra a/d bits on the new ptes where previously they were not set, >>> is fine - setting access bit when it was not set is not an incorrectness >>> problem but will only possibly delay the reclaim of the page mapped by >>> the pte (which is in fact intended because the kernel just operated on this >>> region via mprotect()!). Setting dirty bit when it was not set is again >>> not an incorrectness problem but will only possibly force an unnecessary >>> writeback. >>> >>> So now we need to reason whether something can go wrong via >>> can_change_pte_writable(). The pte_protnone, pte_needs_soft_dirty_wp, >>> and userfaultfd_pte_wp cases are solved due to uniformity in the >>> corresponding bits guaranteed by the flag combination. The ptes all >>> belong to the same VMA (since callers guarantee that [start, end) will >>> lie within the VMA) therefore the conditional based on the VMA is also >>> safe to batch around. >>> >>> Since the dirty bit on the PTE really is just an indication that the folio >>> got written to - even if the PTE is not actually dirty but one of the PTEs >>> in the batch is, the wp-fault optimization can be made. Therefore, it is >>> safe to batch around pte_dirty() in can_change_shared_pte_writable() >>> (in fact this is better since without batching, it may happen that >>> some ptes aren't changed to writable just because they are not dirty, >>> even though the other ptes mapping the same large folio are dirty). >>> >>> To batch around the PageAnonExclusive case, we must check the corresponding >>> condition for every single page. Therefore, from the large folio batch, >>> we process sub batches of ptes mapping pages with the same >>> PageAnonExclusive condition, and process that sub batch, then determine >>> and process the next sub batch, and so on. Note that this does not cause >>> any extra overhead; if suppose the size of the folio batch is 512, then >>> the sub batch processing in total will take 512 iterations, which is the >>> same as what we would have done before. >>> >>> For pte_needs_flush(): >>> >>> ppc does not care about the a/d bits. >>> >>> For x86, PAGE_SAVED_DIRTY is ignored. We will flush only when a/d bits >>> get cleared; since we can only have extra a/d bits due to batching, >>> we will only have an extra flush, not a case where we elide a flush due >>> to batching when we shouldn't have. >>> >>> Signed-off-by: Dev Jain >> >> >> I wanted to review this, but looks like it's already upstream and I suspect >> it's buggy (see the upstream report I cc'ed you on) > > Please excuse my laziness, but do you have a link to the report? I was lazy :) https://lkml.kernel.org/r/68930511.050a0220.7f033.003a.GAE@google.com > I've > been looking at some oddities on arm64 coming back from some of the CI > systems and was heading in the direction of a recent mm regression > judging by the first-known-bad-build in linux-next. > > https://lore.kernel.org/r/CA+G9fYumD2MGjECCv0wx2V_96_FKNtFQpT63qVNrrCmomoPYVQ@mail.gmail.com Hm, mprotect seems to be involved. So it might or might not correlate. -- Cheers, David / dhildenb