From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64415C6377D for ; Thu, 22 Jul 2021 16:55:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3004B6052B for ; Thu, 22 Jul 2021 16:55:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3004B6052B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iOcvG1lKZPEU45a1aEdUeAhVVOCXf7ZDowAD0s+Merk=; b=gvwHJf81GoO704GkQkqNrdDvTc 3VUWXS3Hqfa67KoOkYd+afnkmF5PsQzfuAa7johHkn4XhSTQw0MTXuFEbehs86vQ9diooQVHjLEsi ctTVgk000C/cJvE4fiCL7LMZo6e8LTjJxKyQMP0pQ6/QpWUrvDpaYn3pv8IDyzfqi7t2FuWDsohXl I4bJnbWwS2O+eKgx5BcYzzFp6ld3p1mCnVU1atj5faBGWN2suU/XQOfNkm5stwDV3goxWTwS2/kmD 2tFloqXNs1gigxz3V+MZnxuR/nT1xj6oHqBWPWFYLayzpyZf6mAzLBAqN0xt/f//o3/t64A21PIVu EwttFCSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6bxv-002EBd-Cy; Thu, 22 Jul 2021 16:54:31 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6bxd-002E6y-5A for linux-arm-kernel@lists.infradead.org; Thu, 22 Jul 2021 16:54:16 +0000 Received: from unknown (HELO iyokan2-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 23 Jul 2021 01:54:12 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan2-ex.css.socionext.com (Postfix) with ESMTP id 6FC982083C46; Fri, 23 Jul 2021 01:54:12 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 23 Jul 2021 01:54:12 +0900 Received: from yuzu2.css.socionext.com (yuzu2 [172.31.9.57]) by iyokan2.css.socionext.com (Postfix) with ESMTP id ED269B632B; Fri, 23 Jul 2021 01:54:11 +0900 (JST) Received: from [10.212.30.202] (unknown [10.212.30.202]) by yuzu2.css.socionext.com (Postfix) with ESMTP id 2C500B1D52; Fri, 23 Jul 2021 01:54:11 +0900 (JST) Subject: Re: [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER To: =?UTF-8?Q?Pali_Roh=c3=a1r?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Bjorn Helgaas , Rob Herring , Jingoo Han , Gustavo Pimentel , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , linux-arm-kernel@lists.infradead.org References: <1603848703-21099-4-git-send-email-hayashi.kunihiko@socionext.com> <20201124232037.GA595463@bjorn-Precision-5520> <20201125102328.GA31700@e121166-lin.cambridge.arm.com> <20210718005109.6xwe3z7gxhuop5xc@pali> From: Kunihiko Hayashi Message-ID: <2dfa5ec9-2a33-ae72-3904-999d8b8a2f71@socionext.com> Date: Fri, 23 Jul 2021 01:54:10 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210718005109.6xwe3z7gxhuop5xc@pali> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210722_095413_506768_FE53AC39 X-CRM114-Status: GOOD ( 60.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Pali. On 2021/07/18 9:51, Pali Rohar wrote: > Hello Kunihiko! Now I found also this older email... > > On Friday 27 November 2020 21:02:05 Kunihiko Hayashi wrote: > > Hi Bjorn Lorenzo, > > > > On 2020/11/25 19:23, Lorenzo Pieralisi wrote: > > > On Tue, Nov 24, 2020 at 05:20:37PM -0600, Bjorn Helgaas wrote: > > > > On Wed, Oct 28, 2020 at 10:31:43AM +0900, Kunihiko Hayashi wrote: > > > > > This patch adds misc interrupt handler to detect and invoke PME/AER event. > > > > > > > > > > In UniPhier PCIe controller, PME/AER signals are assigned to the same > > > > > signal as MSI by the internal logic. These signals should be detected by > > > > > the internal register, however, DWC MSI handler can't handle these signals. > > > > > > > > I don't know what "PME/AER signals are assigned to the same signal as > > > > MSI" means. > > > > > > The host controller embeds an interrupt-controller whose IRQ wire output > > > is cascaded into the main interrupt controller. > > > > > > The host-bridge embedded controller receives MSI writes from devices > > > and it turns them into an edge IRQ into the main interrupt controller. > > > > > > To ack/mask the MSIs at host contoller interrupt controller level, there > > > is a control register in the host controller that needs handling upon > > > IRQ reception. > > > > Thanks for explaining that. > > In my understanding, PME/AER signals are cascaded to MSI by embedded > > interrupt controller (not "assigned"). > > > > > > > The *RP* (and AFAIU the RP *only*) signals the PME/AER MSI using the > > > same wire to the main interrupt controller but its ack/mask is handled > > > by a different bit in the host bridge control register above, therefore > > > the cascaded IRQ isr needs to know which virq it is actually handling > > > to ack/mask accordingly. > > > > Sorry what is RP? Root complex or something? > > RP = Root Port > > In lspci output you can find it as "root" of the tree topology and > should have "PCI bridge" class/name. Ok, I understand. > > > > IMO this should be modelled with a separate IRQ domain and chip for > > > the root port (yes this implies describing the root port in the dts > > > file with a separate msi-parent). > > > > > > This series as it stands is a kludge. > > > > I see. However I need some time to consider the way to separate IRQ domain. > > Is there any idea or example to handle PME/AER with IRQ domain? > > Seems that you are dealing with very similar issues as me with aardvark > driver. > > As an inspiration look at my aardvark patch which setup separate IRQ > domain for PME, AER and HP interrupts: > https://lore.kernel.org/linux-pci/20210506153153.30454-32-pali@kernel.org/ > > Thanks to custom driver map_irq function, it is not needed to describe > root port with separate msi-parent in DTS. I need to understand your solution, though, this might be the same situation as my driver. > > > > I'm trying to figure out if this is talking about PME/AER MSI vector > > > > numbers (probably not) > > Bjorn, see my email, based on my experience with aardvark controller I > think they are MSI vector numbers, but controller instead uses own > proprietary way how to signal PME and AER interrupts. > https://lore.kernel.org/linux-pci/20210718002614.3l74hlondwgthuby@pali/ > > > > > or some internal wire that's not > > > > architecturally visible or what. > > > > > > > > Probably also not related to the fact that PME, hotplug, and bandwidth > > > > notifications share the same MSI/MSI-X vector. > > > > > > > > Is this something that's going to be applicable to all the DWC-based > > > > drivers? > > > > I think that this feature depends on the vendor specification. > > At least, the registers to control or check these signals are implemented > > in the vendor's logic. > > > > > > > > > DWC MSI handler calls .msi_host_isr() callback function, that detects > > > > > PME/AER signals with the internal register and invokes the interrupt > > > > > with PME/AER vIRQ numbers. > > > > > > > > > > These vIRQ numbers is obtained from portdrv in uniphier_add_pcie_port() > > > > > function. > > > > > > > > > > Cc: Marc Zyngier > > > > > Cc: Jingoo Han > > > > > Cc: Gustavo Pimentel > > > > > Cc: Lorenzo Pieralisi > > > > > Signed-off-by: Kunihiko Hayashi > > > > > Reviewed-by: Rob Herring > > > > > --- > > > > > drivers/pci/controller/dwc/pcie-uniphier.c | 77 +++++++++++++++++++++++++----- > > > > > 1 file changed, 66 insertions(+), 11 deletions(-) > > > > > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c > > > > > index 4817626..237537a 100644 > > > > > --- a/drivers/pci/controller/dwc/pcie-uniphier.c > > > > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > > > > @@ -21,6 +21,7 @@ > > > > > #include > > > > > #include "pcie-designware.h" > > > > > +#include "../../pcie/portdrv.h" > > > > > #define PCL_PINCTRL0 0x002c > > > > > #define PCL_PERST_PLDN_REGEN BIT(12) > > > > > @@ -44,7 +45,9 @@ > > > > > #define PCL_SYS_AUX_PWR_DET BIT(8) > > > > > #define PCL_RCV_INT 0x8108 > > > > > +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) > > > > > #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) > > > > > +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) > > > > > #define PCL_CFG_BW_MGT_STATUS BIT(4) > > > > > #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) > > > > > #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) > > > > > @@ -68,6 +71,8 @@ struct uniphier_pcie_priv { > > > > > struct reset_control *rst; > > > > > struct phy *phy; > > > > > struct irq_domain *legacy_irq_domain; > > > > > + int aer_irq; > > > > > + int pme_irq; > > > > > }; > > > > > #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) > > > > > @@ -167,7 +172,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) > > > > > static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) > > > > > { > > > > > - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); > > > > > + u32 val; > > > > > + > > > > > + val = PCL_RCV_INT_ALL_ENABLE; > > > > > + if (pci_msi_enabled()) > > > > > + val |= PCL_RCV_INT_ALL_INT_MASK; > > > > > + else > > > > > + val |= PCL_RCV_INT_ALL_MSI_MASK; > > > > > > > > I'm confused about how this works. Root Ports can signal AER errors > > > > with either INTx or MSI. This is controlled by the architected > > > > Interrupt Disable bit and the MSI/MSI-X enable bits (I'm looking at > > > > PCIe r5.0, sec 6.2.4.1.2). > > > > > > > > The code here doesn't look related to those bits. Does this code mean > > > > that if pci_msi_enabled(), the Root Port will always signal with MSI > > > > (if MSI Enable is set) and will *never* signal with INTx? > > > > According to the spec sheet, we need to set interrupt enable bit for either > > INTx or MSI, the other bit should be reset. These bits are in config space > > and handled by the framework. > > Is spec sheet available publicly? Sorry the spec sheet isn't open to the public. Currently initial configuration is to use MSI, and I assume MSI interrupt is used as default. Thank you, --- Best Regards Kunihiko Hayashi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel