From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1D92C433E1 for ; Mon, 13 Jul 2020 12:43:12 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7E1ED2072D for ; Mon, 13 Jul 2020 12:43:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="NmWXR3gG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7E1ED2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9c9qq2uXxiXztn4ziOpig7/5iHtMBbdk+qNVdhvvLso=; b=NmWXR3gGi5V781uhn/9aJN6KT luTDWAiDEa3YLrYEUCQV6xsrWYjuXvggO6WC9ZAGDUm2X47eHHfdbFji5oh/4fQxfOsPRqb51OVmv jioCGIXNOpGLTes1hARVraWYYZuw/vYwXQtGysLpNkLinLEVb3cr48OD0NpnG+uJsnDbj1J81p1ZO n+GZCtQtVdYSx02qzAr6dTEaWClnV1Wkl0noqUrLzi4TZAGVkG1I5Cu9dpu8Y+N2AUgVOgm3bwZgm Aczcub9rN0um7HCEN4cfn2RAdouowVQEI9vdo+fyIQqnUbPUU+H6pMZabn5s/nITvuHVldDb0tenq v9/4J8NDg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1juxmK-0001Oh-6O; Mon, 13 Jul 2020 12:41:52 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1juxmH-0001Mx-7I for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2020 12:41:50 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C32079BA0D8FA8D4044F; Mon, 13 Jul 2020 20:41:38 +0800 (CST) Received: from [127.0.0.1] (10.174.186.75) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 13 Jul 2020 20:41:32 +0800 Subject: Re: [PATCH v2 0/2] arm64: tlb: add support for TLBI RANGE instructions To: Catalin Marinas , , , , , , References: <20200710094420.517-1-yezhenyu2@huawei.com> <159440712962.27784.4664678472466095995.b4-ty@arm.com> <20200713122123.GC15829@gaia> From: Zhenyu Ye Message-ID: <2edcf1ce-38d4-82b2-e500-51f742cae357@huawei.com> Date: Mon, 13 Jul 2020 20:41:31 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200713122123.GC15829@gaia> X-Originating-IP: [10.174.186.75] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200713_084149_572811_5D466248 X-CRM114-Status: GOOD ( 15.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, xiexiangyou@huawei.com, zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Catalin, On 2020/7/13 20:21, Catalin Marinas wrote: > On Fri, Jul 10, 2020 at 08:11:19PM +0100, Catalin Marinas wrote: >> On Fri, 10 Jul 2020 17:44:18 +0800, Zhenyu Ye wrote: >>> NOTICE: this series are based on the arm64 for-next/tlbi branch: >>> git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/tlbi >>> >>> -- >>> ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a >>> range of input addresses. This series add support for this feature. >>> >>> [...] >> >> Applied to arm64 (for-next/tlbi), thanks! >> >> [1/2] arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature >> https://git.kernel.org/arm64/c/a2fd755f77ff >> [2/2] arm64: tlb: Use the TLBI RANGE feature in arm64 >> https://git.kernel.org/arm64/c/db34a081d273 > > I'm dropping these two patches from for-next/tlbi and for-next/core. > They need a check on whether binutils supports the new "tlbi rva*" > instructions, otherwise the build mail fail. > > I kept the latest incarnation of these patches on devel/tlbi-range for > reference. > Should we add a check for the binutils version? Just like: diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fad573883e89..d5fb6567e0d2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1300,6 +1300,20 @@ config ARM64_AMU_EXTN correctly reflect reality. Most commonly, the value read will be 0, indicating that the counter is not enabled. +config ARM64_TLBI_RANGE + bool "Enable support for tlbi range feature" + default y + depends on AS_HAS_TLBI_RANGE + help + ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a + range of input addresses. + + The feature introduces new assembly instructions, and they were + support when binutils >= 2.30. + +config AS_HAS_TLBI_RANGE + def_bool $(as-option, -Wa$(comma)-march=armv8.4-a) + endmenu menu "ARMv8.5 architectural features" Then uses the check in the loop: while (pages > 0) { if (!IS_ENABLED(CONFIG_ARM64_TLBI_RANGE) || !cpus_have_const_cap(ARM64_HAS_TLBI_RANGE) || If this is ok, I could send a new series soon. Thanks, Zhenyu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel