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Wed, 17 Jun 2020 13:00:52 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 09EADC433C8; Wed, 17 Jun 2020 13:00:52 +0000 (UTC) Received: from [192.168.0.101] (unknown [124.123.165.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: neeraju) by smtp.codeaurora.org (Postfix) with ESMTPSA id 94577C433C9; Wed, 17 Jun 2020 13:00:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 94577C433C9 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=neeraju@codeaurora.org Subject: Re: Query regarding ERRATUM_1418040 To: Will Deacon , Marc Zyngier References: <1ce7dad5-a981-5968-cc34-7648faea8636@codeaurora.org> <062be27686369d28bd2054a54c307400@misterjones.org> <20200617112542.GB3503@willie-the-truck> From: Neeraj Upadhyay Message-ID: <2ee8b224-250c-88cc-b1a1-3cc503a3a24f@codeaurora.org> Date: Wed, 17 Jun 2020 18:30:47 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200617112542.GB3503@willie-the-truck> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_060206_288454_F8E1D0E6 X-CRM114-Status: GOOD ( 18.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, Sorry for the wrong mail address. On 6/17/2020 4:55 PM, Will Deacon wrote: > On Wed, Jun 17, 2020 at 12:19:16PM +0100, Marc Zyngier wrote: >> On 2020-06-17 09:55, Neeraj Upadhyay wrote: >>> I have query regarding the errata 1418040 [1]. Here, on kernel exit to >>> EL0 64 bit mode, will it always enable ARCH_TIMER_USR_VCT_ACCESS_EN; >>> and override any other erratas, which might require EL0 direct vct >>> access to be disabled for 64 bit also? >> >> So far, I am not aware of any erratum that would require traps of CNTVCT_EL0 >> to EL1 when running AArch64 userspace for CPUs that are affected by >> ARM-1418040. If such an erratum exists, it would have to be handled >> separately. >> >>> Also, this errata applies >>> mitigation for all CPUs (on return to 32 bit EL0), even if, not all >>> cpus are impacted by the errata? >> >> Indeed. There isn't much we can do to avoid it here, unless you want to read >> some per-CPU variable that tells you whether the CPU is affected. This would >> add to the cost of the mitigation , and isn't an appealing prospect. > > Hmm, but in conjunction with the previous point, doesn't this mean if > some CPUs are affected by an erratum which requires CNTVCT trapping for > AArch64 and others are affected by 1418040, then the former won't actually > be trapped? > > Maybe we should preserve ARCH_TIMER_USR_VCT_ACCESS_EN for AArch64 tasks > instead of setting it unconditionally? > > Will > What is the reason for errata being applied on every kernel exit to EL0 and not at process switch point? Thanks Neeraj -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel