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Tue, 19 Mar 2019 03:01:36 -0700 (PDT) Message-ID: <2f8d217befcc4fdec36e5a31947cccfe74ccd49f.camel@baylibre.com> Subject: Re: [PATCH 0/3] clk: meson: add support for PCIE PLL From: Jerome Brunet To: Neil Armstrong Date: Tue, 19 Mar 2019 11:01:34 +0100 In-Reply-To: <20190307141455.23879-1-narmstrong@baylibre.com> References: <20190307141455.23879-1-narmstrong@baylibre.com> User-Agent: Evolution 3.30.5 (3.30.5-1.fc29) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190319_030139_304149_01B7BE75 X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote: > The Amlogic G12A SoCs embeds a dedicated PLL to feed the USB3+PCIE > Combo PHY. This PLL needs a very specific and strict register sequence > in order to correcly enable it and deliver the 100MHz reference clock > to the Analog PHY. > > After lot of trials and errors, and since this PLL will ever feed 100MHz > with a static configuration, it is simpler to setup a dedicated ops > structure with a custom _enable() op applying the init register sequence. > > The rate calculation ops are kept in order to keep the nominal read > ops as-in, but set_rate is removed. > > With this setup, the PLL can be enabled and disable safely and always have > the recommended PLL setup to feed the USB3+PCIE Combo PHY. > > Neil Armstrong (3): > clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL > dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID > clk: meson-g12a: add PCIE PLL clocks > > drivers/clk/meson/clk-pll.c | 26 ++++++ > drivers/clk/meson/clk-pll.h | 1 + > drivers/clk/meson/g12a.c | 118 ++++++++++++++++++++++++++ > drivers/clk/meson/g12a.h | 5 +- > include/dt-bindings/clock/g12a-clkc.h | 1 + > 5 files changed, 150 insertions(+), 1 deletion(-) Well this PLL is indeed a nasty one ;) Acked-by: Jerome Brunet _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel