From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E362AC433DF for ; Mon, 13 Jul 2020 10:09:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A970F20758 for ; Mon, 13 Jul 2020 10:09:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="zCN7mlIb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A970F20758 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:References: To:Subject:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AqlGCP5Aj0gPnyfQi4UVAxlj22KvYGwiskIGRtFRoJQ=; b=zCN7mlIbA3pvS6Db71Ve6QAxF hmq4+D03jluK5r5bLUZt86urAy0pd4OBxVaKrpexGZeu05ERVy/a8eQXMSxE35FHrrgSMwpznVRxY 669tUtNJKInC7D4ruP+n1ACTkJ0W4LKLtYWQ5bD+BExswvyDKZREGb+l+y5Y+xM7QDpdexWH/0Hm+ kP7IcMsnVBI6r7TyhF2+kqx2rFymJEthD2w6CqxbfR69Pu08x3peyJaU3RbtSqhF/NwdRBWQn5Czz L+LpqJAzBy4a81TrlJK92rXUhuZQyq24aBmN7Zb7MEOmhcQYUg32ASLsX2PYJI6AK7od67k2C0Zda ZgGe8jtRQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1juvNp-0005qn-Jl; Mon, 13 Jul 2020 10:08:25 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1juvNm-0005q0-Il for linux-arm-kernel@lists.infradead.org; Mon, 13 Jul 2020 10:08:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1D781FB; Mon, 13 Jul 2020 03:08:21 -0700 (PDT) Received: from [192.168.1.84] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 18D783F7D8; Mon, 13 Jul 2020 03:08:19 -0700 (PDT) From: Steven Price Subject: Re: [PATCH v6 02/26] arm64: mte: CPU feature detection and initial sysreg configuration To: Catalin Marinas , linux-arm-kernel@lists.infradead.org References: <20200703153718.16973-1-catalin.marinas@arm.com> <20200703153718.16973-3-catalin.marinas@arm.com> Message-ID: <2fb4b560-fb2f-7689-05f7-d908b55cd1eb@arm.com> Date: Mon, 13 Jul 2020 11:08:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200703153718.16973-3-catalin.marinas@arm.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200713_060822_680015_41EA984F X-CRM114-Status: GOOD ( 17.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Will Deacon , Suzuki K Poulose , Szabolcs Nagy , Andrey Konovalov , Kevin Brodsky , linux-mm@kvack.org, Andrew Morton , Vincenzo Frascino , Peter Collingbourne , Dave P Martin Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/07/2020 16:36, Catalin Marinas wrote: > From: Vincenzo Frascino > > Add the cpufeature and hwcap entries to detect the presence of MTE on > the boot CPUs (primary and secondary). Any late secondary CPU not > supporting the feature, if detected during boot, will be parked. > > In addition, add the minimum SCTLR_EL1 and HCR_EL2 bits for enabling > MTE. Without subsequent setting of MAIR, these bits do not have an > effect on tag checking. > > Signed-off-by: Vincenzo Frascino > Co-developed-by: Catalin Marinas > Signed-off-by: Catalin Marinas > Cc: Will Deacon > Cc: Suzuki K Poulose This commit causes the feature bit to be exposed to a guest, but we don't at this point have any way of handling a guest which attempts to use MTE. This is 'fixed' by the first patch of my KVM MTE series[1], but perhaps the chunk modifying arch/arm64/kvm/sys_regs.c (see below) should be included here instead? That way we hide the feature until we're ready for a guest with MTE support. Steve [1] https://lore.kernel.org/r/20200713100102.53664-2-steven.price@arm.com ----8<---- diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index baf5ce9225ce..5ca974c93bd4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1104,6 +1104,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, if (!vcpu_has_sve(vcpu)) val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); + } else if (id == SYS_ID_AA64PFR1_EL1) { + val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | (0xfUL << ID_AA64ISAR1_API_SHIFT) | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel