From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B1E7C433FE for ; Wed, 2 Nov 2022 10:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TAEPrPSxNjYcOU01nXOpmbmAIg3Su6nNYtQENsGitn8=; b=n2GohQoxhz4fjU z8R76J1MEIOMkRi/wX2btJpr+YYTOTHEu2iepa+g05wThr7Tq3f3q0FbMp3txNNFyVtVLyXkbC4ij cugfeqDrfGU6/t8tV6VGk06k+zEdjaLstfohkL/LHz3Lhq1enCRtGkqjc3GgxlfsRq51YeN3Sif/F o9jcSgros0MnVpxwkQpPqa9Cq3nGXX3I5j75Sdsd+ruEy0yWLGjrUzU3Dh+hhuSz9b2olLlAmodoP PZLpyx5AB/x0EarAbJii/1829My2kGd+kUkuH1XShpVb/1YGIsJubOf0nGlWtuHP70R/rkcAtCvSd DfXdA6b6K+HH6ulUKynQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqBHL-00AaLw-54; Wed, 02 Nov 2022 10:47:27 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqBHH-00AaJN-Dx for linux-arm-kernel@lists.infradead.org; Wed, 02 Nov 2022 10:47:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 953BF1FB; Wed, 2 Nov 2022 03:47:27 -0700 (PDT) Received: from [10.163.38.225] (unknown [10.163.38.225]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BAC823F5A1; Wed, 2 Nov 2022 03:47:19 -0700 (PDT) Message-ID: <30067bb4-ebd9-cbfd-3003-7a8b923e5053@arm.com> Date: Wed, 2 Nov 2022 16:17:18 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH 1/8] arm64: cpufeature: Fix the visibility of compat hwcaps To: James Morse , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Suzuki K Poulose References: <20221026055813.13484-1-amit.kachhap@arm.com> <20221026055813.13484-2-amit.kachhap@arm.com> <54728fb0-7ae7-ed09-86bf-19c60b502081@arm.com> Content-Language: en-US From: Amit Kachhap In-Reply-To: <54728fb0-7ae7-ed09-86bf-19c60b502081@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_034723_624181_3C66B1EC X-CRM114-Status: GOOD ( 20.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 10/26/22 20:45, James Morse wrote: > Hi Amit, > > (CC: +Suzuki) > > On 26/10/2022 06:58, Amit Daniel Kachhap wrote: >> Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the >> sysreg visible to user-space") forced the hwcaps to use sanitised >> user-space view of the id registers. However, the ID register structures >> used to select few compat cpufeatures (vfp, crc32, ...) are masked and >> hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32 >> personality. > > Oops - I didn't check the 32bit ones. Thanks for catching this! > > >> Add the ID register structures explicitly and set them as visible for >> the compat hwcaps. > > While 32bit user-space can't access these, 64bit with the personality set now can. > I don't think that's a problem. ok, Nice that this patch fixes other issues also which I didn't thought about. > > > Is there a separate posting of this patch on its own? (do I need to reply there too?) > Mixing fixes with a new-feature series makes the maintainers job harder. Its best to post > fixes separately so they can be treated more urgently than features. > > >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 6062454a9067..43e5b43ef550 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -428,6 +428,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { >> ARM64_FTR_END, >> }; >> >> +static const struct arm64_ftr_bits ftr_mvfr0[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0), >> + ARM64_FTR_END, >> +}; >> + >> +static const struct arm64_ftr_bits ftr_mvfr1[] = { >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0), >> + ARM64_FTR_END, >> +}; > > As these two no longer use ftr_generic_32bits[], could you update the comment above > ftr_generic_32bits[] which lists the id registers that use it? I just send the v2 with your suggestion. Looks like comment were already inconsistent. > > >> static const struct arm64_ftr_bits ftr_mvfr2[] = { >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), >> @@ -458,10 +482,10 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = { >> >> static const struct arm64_ftr_bits ftr_id_isar5[] = { >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), >> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), >> ARM64_FTR_END, >> }; >> @@ -645,8 +669,8 @@ static const struct __ftr_reg_entry { >> ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), >> >> /* Op1 = 0, CRn = 0, CRm = 3 */ >> - ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), >> - ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), >> + ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), >> + ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), >> ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), >> ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), >> ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), > > Reviewed-by: James Morse Thanks for reviewing. Amit > > > Thanks, > > James _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel