Re: [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller

[Andre Przywara <andre.przywara@arm.com>]

Hi Pablo,

On 9/23/26 22:16, Pablo Mazzini wrote:
> One controller at 0x01c20800 with four external interrupt banks.
> 
> Signed-off-by: Pablo Mazzini <pmazzini@gmail.com>
> ---
>   .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++

Why is this a new file? Can't you just add the new compatible string to 
the existing allwinner,sun4i-a10-pinctrl.yaml binding?

Cheers,
Andre

P.S. Since we have seen this a lot lately: please wait with a new 
version of your series for a few days, to allow other people to comment, 
and to allow discussions to settle down. Not everyone can respond quickly.

>   1 file changed, 108 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml
> new file mode 100644
> index 000000000000..806da97ab708
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner B288 Pin Controller
> +
> +maintainers:
> +  - Chen-Yu Tsai <wens@csie.org>
> +  - Jernej Skrabec <jernej.skrabec@gmail.com>
> +
> +properties:
> +  compatible:
> +    const: allwinner,sun8i-b288-pinctrl
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    description:
> +      One interrupt per bank of external interrupt capable pins.
> +    maxItems: 4
> +
> +  clocks:
> +    items:
> +      - description: Bus Clock
> +      - description: High Frequency Oscillator
> +      - description: Low Frequency Oscillator
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: hosc
> +      - const: losc
> +
> +  gpio-controller: true
> +  interrupt-controller: true
> +  gpio-line-names: true
> +
> +  "#gpio-cells":
> +    const: 3
> +
> +  "#interrupt-cells":
> +    const: 3
> +
> +patternProperties:
> +  "-pins$":
> +    type: object
> +    $ref: /schemas/pinctrl/pincfg-node.yaml#
> +    additionalProperties: false
> +
> +    properties:
> +      pins: true
> +      function: true
> +      bias-pull-up: true
> +      bias-pull-down: true
> +      bias-disable: true
> +      drive-strength:
> +        enum: [10, 20, 30, 40]
> +
> +    required:
> +      - pins
> +      - function
> +
> +  "^vcc-p[bcdfg]-supply$":
> +    description:
> +      Power supplies for pin banks.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - gpio-controller
> +  - "#gpio-cells"
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/sun8i-b288-ccu.h>
> +
> +    pio: pinctrl@1c20800 {
> +        compatible = "allwinner,sun8i-b288-pinctrl";
> +        reg = <0x01c20800 0x400>;
> +        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> +        clock-names = "apb", "hosc", "losc";
> +        gpio-controller;
> +        #gpio-cells = <3>;
> +        interrupt-controller;
> +        #interrupt-cells = <3>;
> +
> +        mmc0_pins: mmc0-pins {
> +            pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> +            function = "sdc0";
> +            drive-strength = <30>;
> +            bias-pull-up;
> +        };
> +    };