From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76449C433DF for ; Thu, 6 Aug 2020 12:21:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4417D22D03 for ; Thu, 6 Aug 2020 12:21:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oeZ0slrY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4417D22D03 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bsc6tNucahR6ZfQQ2kh1sIF0Ejcnz5B2gGcqIgWRrDg=; b=oeZ0slrYo2mBPsiSykIk81ear /ahuKE/hfMuV4QvPpClNrKd2Rtt/3Kmw+/qrWrUl732MEWI1rxycaXOz4iDV8D7GX+DZeA9xdUQqW j0Ln1iC7B+JuZ+x+JZi4xVHcFuxsKU93HkzVJSvaqL2Md0Erj2Rn3NiXnsPA7iPBly4k+GfT6Ozkk rpQVFP98OMHieCUIA8MQl22uZQiEy69ncXQIjS7yrqnSO0wWke07xFfuRofUv32KpvLjr8Q2gqrnN K2HQy7nR66pM8x0KzBbo7bq5DSobkuIqFFPyr5WfyPuoiOeHygwnMoPcnePXq3wpfyOQorj7qArTe iCX8JZuiQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3dMY-0000HH-BF; Thu, 06 Aug 2020 10:43:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3dMV-0000Gn-Fr for linux-arm-kernel@lists.infradead.org; Thu, 06 Aug 2020 10:43:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4EBEF113E; Thu, 6 Aug 2020 03:42:58 -0700 (PDT) Received: from [192.168.2.22] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF8613F9AB; Thu, 6 Aug 2020 03:42:57 -0700 (PDT) Subject: Re: [boot-wrapper][PATCH] aarch64: Enable SPE for the non-secure world To: Alexandru Elisei , Mark Rutland References: <20200731094443.11564-1-alexandru.elisei@arm.com> From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Organization: ARM Ltd. Message-ID: <3123be0d-2536-473f-8918-bf3e9a75979b@arm.com> Date: Thu, 6 Aug 2020 11:42:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200731094443.11564-1-alexandru.elisei@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200806_064303_580839_62E5E2B4 X-CRM114-Status: GOOD ( 19.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 31/07/2020 10:44, Alexandru Elisei wrote: Hi, > MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the > profiling buffer to use non-secure memory and to permit direct register > accesses from the non-secure world. > > So far, we haven't programmed MDCR_EL3 explicitly even though there are > other fields which reset to an UNKNOWN value. The majority of those, when > cleared, allow lower exception levels to use the features they control; for > the other fields we don't have support yet. Reset the register to zero > with the exception of MDCR_EL3.NSPB. > > Signed-off-by: Alexandru Elisei > --- > Tested on the model, with ARMv8.2 enabled and disabled (no SPE present). > > arch/aarch64/boot.S | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 74705cded338..f821b0175d4b 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -55,6 +55,17 @@ _start: > > msr cptr_el3, xzr // Disable copro. traps to EL3 > > + mov x0, xzr > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #32, #4 > + cbz x1, 1f > + > + // Enable SPE for the non-secure world. > + ldr x1, =(0x3 << 12) > + orr x0, x0, x1 Just a nit, but 0x3000 is one of the (few) immediate patterns that can be encoded directly in ORR. So you can save the ldr. Other than that: Reviewed-by: Andre Przywara Cheers, Andre > + > +1: msr mdcr_el3, x0 // Disable traps to EL3 > + > mrs x0, id_aa64pfr0_el1 > ubfx x0, x0, #32, #4 // SVE present? > cbz x0, 1f // Skip SVE init if not > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel