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X-IronPort-AV: E=Sophos;i="5.97,276,1669071600"; d="scan'208";a="28889041" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 06 Feb 2023 12:54:50 +0100 Received: from steina-w.localnet (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 41641280056; Mon, 6 Feb 2023 12:54:50 +0100 (CET) From: Alexander Stein To: Marco Felsch Cc: Jonathan Cameron , Cai Huoqing , Haibo Chen , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam , devicetree@vger.kernel.org, linux-iio@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/1] dt-bindings: iio: adc: add missing vref-supply Date: Mon, 06 Feb 2023 12:54:47 +0100 Message-ID: <3215933.aeNJFYEL58@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20230204001333.ywrkty3an3cbuq33@pengutronix.de> References: <20230131101323.606931-1-alexander.stein@ew.tq-group.com> <3214924.aeNJFYEL58@steina-w> <20230204001333.ywrkty3an3cbuq33@pengutronix.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_035456_285157_BD61D889 X-CRM114-Status: GOOD ( 43.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marco, Am Samstag, 4. Februar 2023, 01:13:33 CET schrieb Marco Felsch: > HI Alexander, > > On 23-02-03, Alexander Stein wrote: > > Am Freitag, 3. Februar 2023, 15:12:17 CET schrieb Marco Felsch: > > > Hi, > > > > > > On 23-02-03, Alexander Stein wrote: > > > > > > ... > > > > > > > > > > > > + vref-supply: > > > > > > > > > + description: External ADC reference voltage supply on > > > > > > > > > VREFH > > > > > > > > > pad. > > > > > > > > > > > > > > > > Please add it to the list of required properties, we can > > > > > > > > remove it > > > > > > > > as > > > > > > > > soon as the driver has support for the internal reference > > > > > > > > voltages. > > > > > > > > > > > > > > I was thinking in doing so before as well. But DT describes the > > > > > > > hardware, and this ADC apparently would be functioning without a > > > > > > > reference voltage on that pad, using a different one. What the > > > > > > > driver > > > > > > > actual does is a different matter.> > > > > > > > > > > > > I have also thought about it first but than I checked the RM which > > > > > > says > > > > > > that "multi-reference selection" is chip dependent. > > > > > > > > Nice for pointing this out. I wasn't aware that there are differences. > > > > > > > > > Oh goody. So is it detectable? > > > > > > > > That's my problem. I didn't find any source of information which chips > > > > do > > > > support multiple references and which don't. > > > > Marco, do you have some information on this? > > > > > > You can download the RM from the NXP website but you need an account for > > > it: > > > https://www.nxp.com/products/processors-and-microcontrollers/arm-process > > > ors/ > > > i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8-fami > > > ly-ar > > > m-cortex-a53-cortex-a72-virtualization-vision-3d-graphics-4k-video:i.MX > > > 8 > > > > > > Or is this the wrong model? The naming scheme is quite confusing to me. > > > > That's i.MX8 (imx8qm), the bindings are for i.MX8X (imx8qxp/imx8dxp). But > > I > > assume the ADC is similar/identical. > > > > > > > If we are going to stick to a single compatible rather than adding > > > > > them > > > > > for > > > > > the variants with and without this feature, should probably add a > > > > > note > > > > > at > > > > > least to say it is required for some parts. > > > > > > > > That's a good idea. I'm okay with that, until there is more > > > > information > > > > available. > > > > > > According the RM there is a bit which can be read: Multi Vref > > > Implemented (MVI). > > > > Ah, nice. So there is a hardware feature. From the RM I have available it > > is set for both imx8qm and imx8qxp. Given that I will not mark this as > > required, but add a comment regarding this feature bit. > > Can you check the comments about the refsel please? Since this is the > important part. Since the RM above states that this bit will indicate a > multiref device but it can also the case that, you have a chip with just > on ref selection option (external). I can't check this since I don't > have the RM for this. @NXP can you give us more information please? I would assume if MVI is 0 REFSEL should be considered reserved. Both imx8qm and imx8qxp have MVI set, even imx1170 has this bit set. So I am not aware of any SoC with MVI not being set. Best regards, Alexander _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel