From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47A2EC43334 for ; Thu, 7 Jul 2022 06:21:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nsX8frA8K0JM03lWAsUFFMdRys5a8pM03WGUN99W0/k=; b=ap795N9QpfxcL1 M7bTUGpR3h7V1Vb+iQqr0tbDyyEBHljyVUBwj3aGJON5t3cCpBWCwnltvFc+FNMpnP0QCBfXqTXn4 K7RPIC1dgMS9otqhO6oUM+aAcw/uVq8q+iaeTp3dPOjhxBlt5/mSEK2Gc7ELNNdPp3nYkYezGRRlS Xu2i/rjO6/gh51vIPt+zlibKRKQJkhJ3d/ajDUIE3n1n7VGoaPj6yvZRzTBnYKYvPXGzlA/zUuJH3 2ihweBqxtbBj/lk1NZw+ZlUT+wQhyp4uY3vxVBIlQT4fYORt/wHqAuyWRj0UwFpGZqNJvyterxcVX +r5uY/PMDlpFXCcrjH0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9KsK-00DytE-T3; Thu, 07 Jul 2022 06:20:33 +0000 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9KsH-00Dyp4-0y for linux-arm-kernel@lists.infradead.org; Thu, 07 Jul 2022 06:20:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657174828; x=1688710828; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=0GncP1lP/UKCHyowwfddoOYDjFybJCdgKqH6YR5zIuI=; b=fVku/7afX3Fs7HgnVOhdJrtDCTehTpx8udiXnIuSlXfAklvL53Qm4zJ+ L37fKIua/3A6f5lmBudyUQ6L9nO+dMM7p2TOOCrUeFcnMD8RbfUMI4Sy3 fobUTes8HVvDno81Jbr/huMUnTQmBZmKSdNOzW9Vk9T/rRYrWHcSa0OtO g=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 06 Jul 2022 23:20:22 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2022 23:20:22 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 6 Jul 2022 23:20:21 -0700 Received: from [10.50.36.54] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 6 Jul 2022 23:20:18 -0700 Message-ID: <32306c0d-58cf-b1df-2794-5b1f17e3d062@quicinc.com> Date: Thu, 7 Jul 2022 11:50:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCHv2] iommu/arm-smmu-qcom: Add debug support for TLB sync timeouts Content-Language: en-US To: Will Deacon CC: Robin Murphy , Joerg Roedel , , , , , , Rob Clark , "Bjorn Andersson" References: <20220526041403.9984-1-quic_saipraka@quicinc.com> <20220706115638.GD2403@willie-the-truck> From: Sai Prakash Ranjan In-Reply-To: <20220706115638.GD2403@willie-the-truck> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220706_232029_145835_3FD263B2 X-CRM114-Status: GOOD ( 15.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/6/2022 5:26 PM, Will Deacon wrote: > On Thu, May 26, 2022 at 09:44:03AM +0530, Sai Prakash Ranjan wrote: >> TLB sync timeouts can be due to various reasons such as TBU power down >> or pending TCU/TBU invalidation/sync and so on. Debugging these often >> require dumping of some implementation defined registers to know the >> status of TBU/TCU operations and some of these registers are not >> accessible in non-secure world such as from kernel and requires SMC >> calls to read them in the secure world. So, add this debug support >> to dump implementation defined registers for TLB sync timeout issues. >> >> Signed-off-by: Sai Prakash Ranjan >> --- >> >> Changes in v2: >> * Use scm call consistently so that it works on older chipsets where >> some of these regs are secure registers. >> * Add device specific data to get the implementation defined register >> offsets. >> >> --- >> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 161 ++++++++++++++++++--- >> drivers/iommu/arm/arm-smmu/arm-smmu.c | 2 + >> drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + >> 3 files changed, 146 insertions(+), 18 deletions(-) > If this is useful to you, then I suppose it's something we could support, > however I'm pretty worried about our ability to maintain/scale this stuff > as it is extended to support additional SoCs and other custom debugging > features. > > Perhaps you could stick it all in arm-smmu-qcom-debug.c and have a new > config option for that, so at least it's even further out of the way? > > Will Sounds good to me, will do that. Thanks, Sai _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel