From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED4E2CD11C2 for ; Wed, 10 Apr 2024 07:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6xCj8Qfm0KwDW4z5wVtl/9SZ64p3DueaYlJztRkJp6g=; b=2hmy3TAJ0sk5K+ 5t3pUMyNGKErM6zhTqXteYIRpcgt4Z2DpoUsaMqDH9SNmKFWMrO+NsLLUuXAftbOypZxFxuRdzIxr gXIUDd20WOz0Kt0Jtv73X7hC1Lat637hJIItLDHif6aG8dfQHiD2CppjIgQmjCsFGe+BufNj0Rdtl gCzjL/Rj2Njhie54QOWg9iyw5YMMha+PVfKfZ9cBZrcBc5qwYykVLY1hj8Lr1jZzrF0odiIKmJtqS KYjSDHUvQO/nTWHbDrOrNdbPA5D55n+V27YE6SksVURp6gqoHcSqQuvme6bwb6Z6ejak+kEVjjnQ6 VWvB5nFPhytODooZHFjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruSqD-00000005jwR-0QFo; Wed, 10 Apr 2024 07:57:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruSq9-00000005jsO-2v5H for linux-arm-kernel@lists.infradead.org; Wed, 10 Apr 2024 07:57:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D915B1480; Wed, 10 Apr 2024 00:58:17 -0700 (PDT) Received: from [10.162.43.6] (a077893.blr.arm.com [10.162.43.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 81A413F766; Wed, 10 Apr 2024 00:57:42 -0700 (PDT) Message-ID: <32ddd2a6-22c6-49d2-aebb-da5a2e99748d@arm.com> Date: Wed, 10 Apr 2024 13:27:39 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: tlb: Improve __TLBI_VADDR_RANGE() Content-Language: en-US To: Gavin Shan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, maz@kernel.org, oliver.upton@linux.dev, ryan.roberts@arm.com, apopple@nvidia.com, rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com, yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com, shan.gavin@gmail.com References: <20240405035852.1532010-1-gshan@redhat.com> <20240405035852.1532010-3-gshan@redhat.com> From: Anshuman Khandual In-Reply-To: <20240405035852.1532010-3-gshan@redhat.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240410_005754_006515_0F12BCF2 X-CRM114-Status: GOOD ( 13.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/5/24 09:28, Gavin Shan wrote: > The macro returns the operand of TLBI RANGE instruction. A mask needs > to be applied to each individual field upon producing the operand, to > avoid the adjacent fields can interfere with each other when invalid > arguments have been provided. The code looks more tidy at least with > a mask and FIELD_PREP(). > > Suggested-by: Marc Zyngier > Signed-off-by: Gavin Shan This looks much better. Reviewed-by: Anshuman Khandual > --- > arch/arm64/include/asm/tlbflush.h | 29 ++++++++++++++++++----------- > 1 file changed, 18 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index a75de2665d84..243d71f7bc1f 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -142,17 +142,24 @@ static inline unsigned long get_trans_granule(void) > * EL1, Inner Shareable". > * > */ > -#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \ > - ({ \ > - unsigned long __ta = (baddr); \ > - unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > - __ta &= GENMASK_ULL(36, 0); \ > - __ta |= __ttl << 37; \ > - __ta |= (unsigned long)(num) << 39; \ > - __ta |= (unsigned long)(scale) << 44; \ > - __ta |= get_trans_granule() << 46; \ > - __ta |= (unsigned long)(asid) << 48; \ > - __ta; \ > +#define TLBIR_ASID_MASK GENMASK_ULL(63, 48) > +#define TLBIR_TG_MASK GENMASK_ULL(47, 46) > +#define TLBIR_SCALE_MASK GENMASK_ULL(45, 44) > +#define TLBIR_NUM_MASK GENMASK_ULL(43, 39) > +#define TLBIR_TTL_MASK GENMASK_ULL(38, 37) > +#define TLBIR_BADDR_MASK GENMASK_ULL(36, 0) > + > +#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \ > + ({ \ > + unsigned long __ta = 0; \ > + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > + __ta |= FIELD_PREP(TLBIR_BADDR_MASK, baddr); \ > + __ta |= FIELD_PREP(TLBIR_TTL_MASK, __ttl); \ > + __ta |= FIELD_PREP(TLBIR_NUM_MASK, num); \ > + __ta |= FIELD_PREP(TLBIR_SCALE_MASK, scale); \ > + __ta |= FIELD_PREP(TLBIR_TG_MASK, get_trans_granule()); \ > + __ta |= FIELD_PREP(TLBIR_ASID_MASK, asid); \ > + __ta; \ > }) > > /* These macros are used by the TLBI RANGE feature. */ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel