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Oktober 2024, 13:10:17 CEST schrieb Xu Yang: > Add usb3 phy and controller nodes for imx95. >=20 > Signed-off-by: Xu Yang >=20 > --- > Changes in v2: > - no changes > Changes in v3: > - no changes > Changes in v4: > - reorder nodes > Changes in v5: > - no changes > Changes in v6: > - rebase to latest > Changes in v7: > - no changes > Changes in v8: > - no changes > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 43 ++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/d= ts/freescale/imx95.dtsi > index 03661e76550f..e3faa8462759 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -1473,6 +1473,49 @@ smmu: iommu@490d0000 { > }; > }; > =20 > + usb3: usb@4c010010 { > + compatible =3D "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; > + reg =3D <0x0 0x4c010010 0x0 0x04>, > + <0x0 0x4c1f0000 0x0 0x20>; > + clocks =3D <&scmi_clk IMX95_CLK_HSIO>, > + <&scmi_clk IMX95_CLK_32K>; > + clock-names =3D "hsio", "suspend"; > + interrupts =3D ; > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + ranges; > + power-domains =3D <&scmi_devpd IMX95_PD_HSIO_TOP>; > + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; > + status =3D "disabled"; > + > + usb3_dwc3: usb@4c100000 { > + compatible =3D "snps,dwc3"; > + reg =3D <0x0 0x4c100000 0x0 0x10000>; > + clocks =3D <&scmi_clk IMX95_CLK_HSIO>, > + <&scmi_clk IMX95_CLK_24M>, > + <&scmi_clk IMX95_CLK_32K>; > + clock-names =3D "bus_early", "ref", "suspend"; > + interrupts =3D ; > + phys =3D <&usb3_phy>, <&usb3_phy>; > + phy-names =3D "usb2-phy", "usb3-phy"; > + snps,gfladj-refclk-lpm-sel-quirk; > + snps,parkmode-disable-ss-quirk; Downstream kernel also configures > snps,tx-max-burst =3D /bits/ 8 <4>; > snps,tx-thr-num-pkt =3D /bits/ 8 <1>; is this not needed and omitted on purpose? Best regards, Alexander > + iommus =3D <&smmu 0xe>; > + }; > + }; > + > + usb3_phy: phy@4c1f0040 { > + compatible =3D "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; > + reg =3D <0x0 0x4c1f0040 0x0 0x40>, > + <0x0 0x4c1fc000 0x0 0x100>; > + clocks =3D <&scmi_clk IMX95_CLK_HSIO>; > + clock-names =3D "phy"; > + #phy-cells =3D <0>; > + power-domains =3D <&scmi_devpd IMX95_PD_HSIO_TOP>; > + orientation-switch; > + status =3D "disabled"; > + }; > + > pcie0: pcie@4c300000 { > compatible =3D "fsl,imx95-pcie"; > reg =3D <0 0x4c300000 0 0x10000>, >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/