From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [GIT PULL v2 1/4] ARM: tegra: IOMMU support for v3.19
Date: Thu, 04 Dec 2014 16:03:49 +0100 [thread overview]
Message-ID: <3327156.hTO1VnvNbE@wuerfel> (raw)
In-Reply-To: <20141204144354.GA31464@ulmo.nvidia.com>
On Thursday 04 December 2014 15:43:56 Thierry Reding wrote:
> We discussed this on IRC and come to the conclusion that this approach
> (encoding the table in the driver) was indeed the best for this
> particular type of setup. For the record I'll try to explain the same
> here and provide more details.
Yes, thanks a lot!
> > I was assuming that you'd have one 'struct device' per client in all
> > cases, so you'd have a unique association between a swgroup/id tuple
> > and the device pointer that you pass into the dma-mapping and IOMMU APIs.
>
> The majority of devices have two clients: one for read transactions,
> another for write transactions. These are typically named <module>r and
> <module>w, respectively. But each such module is a single device and
> represented by a single device tree node.
>
> The display controllers are somewhat exceptional in that they only read
> data, so there are no write clients. But they also have a couple of
> clients, one for each display window (or overlay). Like you said, this
> looks really like each client is a unidirectional special-purpose DMA
> master.
>
> Some examples:
>
> HDA: 2 clients: hdar and hdaw
> SATA: 2 clients: satar and satar
> DC: 6 clients: display{0a,0b,0c,hc,t,d}
> DCB: 4 clients: display{0ab,0bb,0cb,hcb}
>
> Each of those is a single IP block, and each has a SWGROUP that contains
> the set of all the memory clients.
Yep
> > > There are patches in the works to add support for EMC frequency scaling
> > > and also latency allowance programming.
> >
> > Ok, I see. The part that I'm missing here is how the client driver
> > knows its number, as you write that we don't have a device node per
> > client. Do you have a particular binding in mind already?
>
> I was thinking that each device tree node would get an additional
> property, maybe something like the below. I'm not sure if it makes sense
> to turn this into a generic binding, given that this is likely to be
> implemented fairly differently on other SoCs, or perhaps other SoCs
> don't even have an equivalent of it.
>
> mc: memory-controller at 70019000 {
> compatible = "nvidia,tegra124-mc";
> ...
>
> #nvidia,memory-client-cells = <1>;
> };
>
> dc at 54200000 {
> compatible = "nvidia,tegra124-dc";
>
> ...
>
> nvidia,memory-client = <&mc 1 &mc 3 &mc 5 &mc 16 &mc 90 &mc 115>;
> };
>
> Maybe we'd even need something like nvidia,memory-client-names so that
> drivers can determine for which specific clients to set the latency
> allowance.
Yes. We'd have to discuss the binding with some of the other SoC maintainers
to see if they might have a use for this too, but this certainly makes
sense.
Arnd
next prev parent reply other threads:[~2014-12-04 15:03 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-21 11:53 [GIT PULL 1/4] ARM: tegra: IOMMU support for v3.19 Thierry Reding
2014-11-21 11:53 ` [GIT PULL 2/4] ARM: tegra: Device tree changes " Thierry Reding
2014-11-26 9:10 ` [GIT PULL v2 " Thierry Reding
2014-11-21 11:53 ` [GIT PULL 3/4] ARM: tegra: Default configuration " Thierry Reding
2014-11-28 21:45 ` Arnd Bergmann
2014-11-21 11:53 ` [GIT PULL 4/4] ARM: tegra: Core code " Thierry Reding
2014-11-28 21:49 ` Arnd Bergmann
2014-12-01 13:19 ` Thierry Reding
2014-11-26 9:10 ` [GIT PULL v2 1/4] ARM: tegra: IOMMU support " Thierry Reding
2014-11-28 22:20 ` Arnd Bergmann
2014-12-01 15:05 ` Thierry Reding
2014-12-01 17:55 ` Arnd Bergmann
2014-12-02 11:51 ` Thierry Reding
2014-12-04 13:36 ` Arnd Bergmann
2014-12-04 14:43 ` Thierry Reding
2014-12-04 15:03 ` Arnd Bergmann [this message]
2014-12-04 15:45 ` [GIT PULL v3 " Thierry Reding
2014-12-04 15:45 ` [GIT PULL v3 2/4] ARM: tegra: Device tree changes " Thierry Reding
2014-12-04 16:24 ` Arnd Bergmann
2014-12-04 16:37 ` Thierry Reding
2014-12-04 16:21 ` [GIT PULL v3 1/4] ARM: tegra: IOMMU support " Arnd Bergmann
2014-12-04 16:36 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3327156.hTO1VnvNbE@wuerfel \
--to=arnd@arndb.de \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox