From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71DB0CCD195 for ; Wed, 22 Oct 2025 09:52:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IRzW4TIfXqA8U8VyFhl4a5nR+JpRyPOHWAWMvoNSBog=; b=P8upCxUVRXEE0AI5Xsz4OG1Gzs q0JU6597EAA/rhj3y9FfO4JjjkRnhiR07DQ6uFXabrvb+OWcJu2dkOMrGEQsqDocB0A4No8hnYWdB KbtvH7fbp6LNtAbLYldMNud6KwHReFfw/Gp98Ad7Qi5YDhkEBLQURSgBdzS612/XLrUTLUSuiBR/g BnBk08HW6Nb07lrO84dCM8phQ3XK+zrGPmYqx3INjQIb23u+LCBhHE6/232+vkWkOtH0F23tDWxVy B9G1HX2WhgrxKLdrbPMfLeq/dzaf+AocIvxN5k7peK+zPTKci3vriQcnNhLytIZJTfPu5sfKYxA9X AAziCBNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBVW7-00000002K2M-3jbb; Wed, 22 Oct 2025 09:52:27 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBVW5-00000002K0A-0x92; Wed, 22 Oct 2025 09:52:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=IRzW4TIfXqA8U8VyFhl4a5nR+JpRyPOHWAWMvoNSBog=; b=fA20BholhvJ7oFwc8aYVXE2OrK QjmyiUqQbpuRqoxZ+ov/1s2x79Oq5rPYjUrhl9DPId2GhGLbZqtiykPQFIvR/6h5tHc58MyrJeV3T 8O3t0i8QBYjRFBJmTVw0E91OigGD6TNXcOoihDOeLxh7R3AYtgHPwRvj/J+bzH2ruAkf2WLUC+5/Z 1wcyMleDF0U1wMB7ysgv16Z0TPkayX3+cE4KSntcTzTnnGiuWNbTucD8PWCP8peCuyioOY9sf3DTp UjAuzab7XyvRpTVIlzGqrQ9oojXWZ7iWnmWupjwZZ8I9f6XY9JgG8Y079cHBJJX8aTHKSiC+JVPG6 PKkkGKRg==; Received: from [141.76.253.241] (helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vBVVt-00027D-MX; Wed, 22 Oct 2025 11:52:13 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org, sugar.zhang@rock-chips.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, zhangqing Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, finley.xiao@rock-chips.com, Conor Dooley Subject: Re: [PATCH v4 2/7] dt-bindings: clock, reset: Add support for rv1126b Date: Wed, 22 Oct 2025 11:52:12 +0200 Message-ID: <3346817.AJdgDx1Vlc@phil> In-Reply-To: <5a551943-141a-4842-a4d0-b66b32cf3e70@rock-chips.com> References: <20251021065232.2201500-1-zhangqing@rock-chips.com> <4463339.ejJDZkT8p0@phil> <5a551943-141a-4842-a4d0-b66b32cf3e70@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251022_025225_307407_2814D866 X-CRM114-Status: GOOD ( 20.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Elaine, Am Mittwoch, 22. Oktober 2025, 05:21:43 Mitteleurop=C3=A4ische Sommerzeit s= chrieb zhangqing: > =E5=9C=A8 2025/10/21 16:38, Heiko Stuebner =E5=86=99=E9=81=93: > > Am Dienstag, 21. Oktober 2025, 08:52:27 Mitteleurop=C3=A4ische Sommerze= it schrieb Elaine Zhang: > >> Add clock and reset ID defines for rv1126b. > >> Also add documentation for the rv1126b CRU core. > >> > >> Signed-off-by: Elaine Zhang > >> Acked-by: Conor Dooley > >> --- > >> .../bindings/clock/rockchip,rv1126b-cru.yaml | 52 +++ > >> .../dt-bindings/clock/rockchip,rv1126b-cru.h | 392 +++++++++++++++++ > >> .../dt-bindings/reset/rockchip,rv1126b-cru.h | 405 ++++++++++++++++= ++ > >> 3 files changed, 849 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,= rv1126b-cru.yaml > >> create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h > >> create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h > >> > >> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-= cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml > >> new file mode 100644 > >> index 000000000000..04b0a5c51e4e > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml > >> @@ -0,0 +1,52 @@ > >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Rockchip RV1126B Clock and Reset Unit > >> + > >> +maintainers: > >> + - Elaine Zhang > >> + - Heiko Stuebner > >> + > >> +description: > >> + The rv1126b clock controller generates the clock and also implement= s a > >> + reset controller for SoC peripherals. > >> + > >> +properties: > >> + compatible: > >> + enum: > >> + - rockchip,rv1126b-cru > >> + > >> + reg: > >> + maxItems: 1 > >> + > >> + "#clock-cells": > >> + const: 1 > >> + > >> + "#reset-cells": > >> + const: 1 > >> + > >> + clocks: > >> + maxItems: 1 > >> + > >> + clock-names: > >> + const: xin24m > > I think we're missing the optional > > > > rockchip,grf: > > $ref: /schemas/types.yaml#/definitions/phandle > > description: > > Phandle to the syscon managing the "general register files" (GR= =46), > > if missing pll rates are not changeable, due to the missing pll > > lock status. > > > > > > because RV1126B_GRF_SOC_STATUS0 contains the PLL lock status. > The pll lock truly uses bit10 of the PLL_CON1 register of CRU and does=20 > not use grf. Does that mean there is no need to increase rockchip,grf=EF= =BC=9F correct ... in that case we don't need the GRF reference. As we're not accessing the GRF. Please also drop the RV1126B_GRF_SOC_STATUS0 constant from the driver in that case. Thanks Heiko