From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCDF4C77B75 for ; Tue, 18 Apr 2023 13:51:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=121EuW+4xZsowYUT0XL+3djWtzDLdSRTI93IRM3GB2s=; b=1nExujEGIyWFX+ 35YejUsRsI70r4YQRzK920PXoxjTKc5MQ+W9qUCnJt7mcjH1X2AcYbPAvvqhODRb7WNKbdV7Kh6q3 TEumnM+YE2rYQleJAbY9xf5m19dSx16jq9NzI9EkrPtab3P6e9dwyusPix35VRgVGrQbt04pQlu8G 6aSJagqbc1x/9XuDYDnSBu8lBhkPwKgMupdF5KEY7HKgnFr+g2CJ6pf24F0Td71dnIp7Iw17WOLbn jUOey8DNeWqg6n4G4zr61Hchm2Q8kJ6T1/i2vKwA8/vtoX5RNkIlz91tVMnSEFV/GFTCMRwB/3iEd RKswjjWbpL7qcUUTFviQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1poljH-002KLM-0h; Tue, 18 Apr 2023 13:50:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1poljA-002KBN-0s for linux-arm-kernel@lists.infradead.org; Tue, 18 Apr 2023 13:50:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1EB31063; Tue, 18 Apr 2023 06:51:05 -0700 (PDT) Received: from [10.1.27.157] (C02CF1NRLVDN.cambridge.arm.com [10.1.27.157]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0F8BC3F587; Tue, 18 Apr 2023 06:50:20 -0700 (PDT) Message-ID: <334f041e-575f-4efe-bfd8-53b7d19f8371@arm.com> Date: Tue, 18 Apr 2023 14:50:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 49/60] arm64: Enable LPA2 at boot if supported by the system Content-Language: en-US To: Ard Biesheuvel , linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland , Anshuman Khandual , Kees Cook References: <20230307140522.2311461-1-ardb@kernel.org> <20230307140522.2311461-50-ardb@kernel.org> From: Ryan Roberts In-Reply-To: <20230307140522.2311461-50-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230418_065036_404635_E01A01A3 X-CRM114-Status: GOOD ( 34.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 07/03/2023 14:05, Ard Biesheuvel wrote: > Update the early kernel mapping code to take 52-bit virtual addressing > into account based on the LPA2 feature. This is a bit more involved than > LVA (which is supported with 64k pages only), given that some page table > descriptor bits change meaning in this case. > > To keep the handling in asm to a minimum, the initial ID map is still > created with 48-bit virtual addressing, which implies that the kernel > image must be loaded into 48-bit addressable physical memory. This is > currently required by the boot protocol, even though we happen to > support placement outside of that for LVA/64k based configurations. > > Enabling LPA2 involves more than setting TCR.T1SZ to a lower value, > there is also a DS bit in TCR that needs to be set, and which changes > the meaning of bits [9:8] in all page table descriptors. Since we cannot > enable DS and every live page table descriptor at the same time, let's > pivot through another temporary mapping. This avoids the need to > reintroduce manipulations of the page tables with the MMU and caches > disabled. > > To permit the LPA2 feature to be overridden on the kernel command line, > which may be necessary to work around silicon errata, or to deal with > mismatched features on heterogeneous SoC designs, test for CPU feature > overrides first, and only then enable LPA2. > > Signed-off-by: Ard Biesheuvel > --- > arch/arm64/include/asm/assembler.h | 8 ++- > arch/arm64/include/asm/cpufeature.h | 18 +++++ > arch/arm64/include/asm/memory.h | 4 ++ > arch/arm64/kernel/head.S | 8 +++ > arch/arm64/kernel/image-vars.h | 1 + > arch/arm64/kernel/pi/map_kernel.c | 70 +++++++++++++++++++- > arch/arm64/kernel/pi/map_range.c | 11 ++- > arch/arm64/kernel/pi/pi.h | 4 +- > arch/arm64/mm/init.c | 2 +- > arch/arm64/mm/mmu.c | 6 +- > arch/arm64/mm/proc.S | 3 + > 11 files changed, 124 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index 55e8731844cf7eb7..d5e139ce0820479b 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -581,11 +581,17 @@ alternative_endif > * but we have to add an offset so that the TTBR1 address corresponds with the > * pgdir entry that covers the lowest 48-bit addressable VA. > * > + * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an > + * additional paging level, and on LPA2/16k pages, we would end up with a root > + * level table with only 2 entries, which is suboptimal in terms of TLB > + * utilization, so there we fall back to 47 bits of translation if LPA2 is not > + * supported. > + * > * orr is used as it can cover the immediate value (and is idempotent). > * ttbr: Value of ttbr to set, modified. > */ > .macro offset_ttbr1, ttbr, tmp > -#ifdef CONFIG_ARM64_VA_BITS_52 > +#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2) > mrs \tmp, tcr_el1 > and \tmp, \tmp, #TCR_T1SZ_MASK > cmp \tmp, #TCR_T1SZ(VA_BITS_MIN) > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 7faf9a48339e7c8c..170e18cb2b4faf11 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -1002,6 +1002,24 @@ static inline bool cpu_has_lva(void) > ID_AA64MMFR2_EL1_VARange_SHIFT); > } > > +static inline bool cpu_has_lpa2(void) > +{ > +#ifdef CONFIG_ARM64_LPA2 > + u64 mmfr0; > + int feat; > + > + mmfr0 = read_sysreg(id_aa64mmfr0_el1); > + mmfr0 &= ~id_aa64mmfr0_override.mask; > + mmfr0 |= id_aa64mmfr0_override.val; > + feat = cpuid_feature_extract_signed_field(mmfr0, > + ID_AA64MMFR0_EL1_TGRAN_SHIFT); > + > + return feat >= ID_AA64MMFR0_EL1_TGRAN_LPA2; > +#else > + return false; > +#endif > +} I wonder if we should rename this to cpu_has_lpa2_stage1()? I currently have a system_supports_lpa2() function, which wraps a system cap, and reports true if BOTH stage1 and stage2 are supported. I suspect this should be renamed to something like system_has_lpa2_stage12() to match? Regardless, in my series, KVM currently decides whether or not to use LPA2 page tables based on system_supports_lpa2(). But I will need to add a new condition whereby if the kernel is using LPA2 (lpa2_is_enabled()) but stage2 reports that LPA2 is not supported then KVM fails to initialize. Otherwise we could end up in a situation where KVM can't map memory passed to it by the kernel. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel