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Tue, 02 Sep 2025 12:56:51 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 582Cuodr029185 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 Sep 2025 12:56:50 GMT Received: from [10.253.38.125] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Tue, 2 Sep 2025 05:56:43 -0700 Message-ID: <335d6661-8719-46d7-89c6-3392fc13f396@quicinc.com> Date: Tue, 2 Sep 2025 20:56:41 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Luo Jie Subject: Re: [PATCH v4 06/10] dt-bindings: clock: Add required "interconnect-cells" property To: Krzysztof Kozlowski CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , "Varadarajan Narayanan" , Georgi Djakov , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Anusha Rao , "Manikanta Mylavarapu" , Devi Priya , Philipp Zabel , "Richard Cochran" , Konrad Dybcio , Catalin Marinas , Will Deacon , , , , , , , , , , , , References: <20250828-qcom_ipq5424_nsscc-v4-0-cb913b205bcb@quicinc.com> <20250828-qcom_ipq5424_nsscc-v4-6-cb913b205bcb@quicinc.com> <20250829-ubiquitous-imaginary-mammoth-d52bde@kuoka> Content-Language: en-US In-Reply-To: <20250829-ubiquitous-imaginary-mammoth-d52bde@kuoka> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzMSBTYWx0ZWRfX58rUtrKpDeG6 9nJEjs6cttA8dPwot1KSSZsLhRHpn3F/cZSyeZ62+jfg7dQfQpDBS0HzqE18XIcwVCjvB7WDesj P/bHiOi7krhVPAGdA56ZxxurD7hG66MXS8P1VsfmZXsX+1L9JonlUsRtHQoSK6sWACYuJmQkXtu d00vyLYQ7/GEUvI5LemFZAadZ68AV8l6aplytq89hiOVju+/EOUcso15Z9YymWFAaQKBJ5N0AYQ N9cV+dUIVcoltdl81jpMxQ2tq7s7oEjyfnfCmGD5KZ7/IrDVXAfTHONRmMhtlxlWKL1k6lk38rk cdvih+mRJ9HnEGz4X+tdSY6gCwj8iTgB9SkYqcg3TeTRAHb/bCFHzwAwlmd7ozwRsLkRIN6FtQ/ 7vSXolz4 X-Authority-Analysis: v=2.4 cv=A8xsP7WG c=1 sm=1 tr=0 ts=68b6e994 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=g-MkapQZPYqtOJljyDYA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: SkBytaGhBcwz6UtUuAqgjW778_jLkguH X-Proofpoint-GUID: SkBytaGhBcwz6UtUuAqgjW778_jLkguH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_04,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300031 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250902_055700_402695_BC9C11DC X-CRM114-Status: GOOD ( 20.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/29/2025 3:37 PM, Krzysztof Kozlowski wrote: > On Thu, Aug 28, 2025 at 06:32:19PM +0800, Luo Jie wrote: >> ICC clocks are always provided by the NSS clock controller of IPQ9574, >> so add interconnect-cells as required DT property. > > Does not make sense. If clocks are always, you require different > property? The '#interconnect-cells' property is mandatory in the DTS so that the client driver such as PPE driver can acquire the ICC clocks from the NSS CC provider. This is already part of the IPQ9574 DTS which is merged. We had missed adding it as 'Required' at that time and fixing it now. I will update the commit message to describe this better in the next version to avoid confusion. > >> >> Fixes: 28300ecedce4 ("dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions") >> Signed-off-by: Luo Jie > > Fixes cannot be in the middle of patchset. > > See submitting patches and your internal guideline explaining it with > great details. > I understand that fixes should not be placed in the middle of a patchset. I will reorder the patches to ensure that all fixes are at the beginning of the series. >> --- >> Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >> index 17252b6ea3be..fc604279114f 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >> @@ -57,6 +57,7 @@ required: >> - compatible >> - clocks >> - clock-names >> + - '#interconnect-cells' > > ABI break without explanation. > > Best regards, > Krzysztof > This property is already present in the current IPQ9574 SoC DTS file which is already merged, and hence no ABI break is introduced for IPQ9574. I will update the commit message in the next version to clarify this.