From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46AE9C021A4 for ; Wed, 12 Feb 2025 17:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+cY47LAqWAXj1BfEuZxsbrq82d0rEj7M6oLMYtXtYDQ=; b=gwszGHD6KxXqUNH3XWYvrg6YDq Zdt72h15eRCmAw3WbuwGvg/1h6ouHFqQWV2Cw6MKFb2WkCfl+vb/1UsAoPGC1tg6GhEk/BxYQmbn6 v+AEvvK8XUqeU/MUmaBoLTgLbwZSM/UJmKuVBCzxXWfnYDxtglQyz9HLaW1D88OzjFdmEgJRFzZA8 Wu+bnkHlUjWTnCS0F6cEIAFVdCZCxJGjVnQbm8D0VQ3k4aZ01V0rEzeuwRr2Y6V4TnsDlPTVFl/Vi CHYxMsG1K/Yda+8dv4BLCcOY31Mm2jgt4W8uOSWwuvmmFT7HAWc0AfGO40BZ8wR6zmcRgv/BifGXE AzbHCkIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tiGGZ-00000008F9G-3XHx; Wed, 12 Feb 2025 17:11:15 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tiFsU-000000089iN-0c6u; Wed, 12 Feb 2025 16:46:23 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id E8DD9A40C0D; Wed, 12 Feb 2025 16:44:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BADD3C4CEE2; Wed, 12 Feb 2025 16:46:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739378781; bh=dBlv29benpRXnHK6aFHmeoFcTFBzZcFMV33Vx/ypJEw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=e1HyDBMdqOGCUvxXYvV+Ko7K2m4FxzxOSSxHOlqRcjl+f3935/0l3rF3nJOydXeUY 6GG/aZtFFY9/eZpYbSCsYxGxJcciAMYPoKB4WQOEWPv3QbHv6MOuKy2i9atXxb+XGe oW5PBZpyDHTVtDsj6VfBhhySSuEppnf3pyZ+N2XmIvPvsAQrBuxTPKpSbQYxXEx2nU AMRf2RwEGOPXxAElqs4uGtn7viYUsqQzzwtgcYa0iMs8DtjXsNOLWt4GIrZwymZ7Ip qaVmfm+Z4VGzjBSo86sPiwwx1mxMO7+YriMGfKsxMarEP6n34EGT5meo5e0itT6wUK vmYnIIqwuvDNQ== Message-ID: <33654180-5488-4601-9103-8e4218c4a198@kernel.org> Date: Wed, 12 Feb 2025 17:46:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files To: Alexander Sverdlin , Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Chao Wei References: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> <20250210220951.1248533-2-alexander.sverdlin@gmail.com> <708cdc497b8474609989395dbf8a0898037a22de.camel@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_084622_323653_73DA57F8 X-CRM114-Status: GOOD ( 16.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/02/2025 10:26, Alexander Sverdlin wrote: > Hi Inochi, Krzysztof, > > On Wed, 2025-02-12 at 08:31 +0800, Inochi Amaoto wrote: >> On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote: >>> Make the peripheral device tree re-usable on ARM64 platform by moving CPU >>> core and interrupt controllers' parts into the respective per-SoC .dtsi >>> files. >>> >>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering >>> into "plic" interrupt-controller numbering. >>> >>> Have a nice refactoring side-effect that "plic" and "clint" "compatible" >>> property is not specified outside of the corresponding device itself. >>> >>> Signed-off-by: Alexander Sverdlin >>> --- >>> Changelog: >>> v2: >>> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU >>> core, interrupt controllers) and spread them among 3 SoC .dtsi files which >>> included cv18xx.dtsi; >>> - define a label for the "soc" node and use it in the newly introduced DTs; >>> >>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi    | 64 ++++++++++++--- >>>  arch/riscv/boot/dts/sophgo/cv1812h.dtsi    | 64 ++++++++++++--- >>>  arch/riscv/boot/dts/sophgo/cv181x.dtsi     |  2 +- >>>  arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++ >>>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi     | 91 ++++++---------------- >>>  arch/riscv/boot/dts/sophgo/sg2002.dtsi     | 64 ++++++++++++--- >>>  6 files changed, 240 insertions(+), 102 deletions(-) >>>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi >>> >>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>> index aa1f5df100f0..eef2884b36f9 100644 >>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>> @@ -3,6 +3,8 @@ >>>   * Copyright (C) 2023 Jisheng Zhang >>>   */ >>>   >>> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) >>> + >>>  #include >>>  #include "cv18xx.dtsi" >>>   >>> @@ -14,22 +16,62 @@ memory@80000000 { >>>   reg = <0x80000000 0x4000000>; >>>   }; >>>   >> >>> - soc { >>> - pinctrl: pinctrl@3001000 { >>> - compatible = "sophgo,cv1800b-pinctrl"; >>> - reg = <0x03001000 0x1000>, >>> -       <0x05027000 0x1000>; >>> - reg-names = "sys", "rtc"; >> >> >>> + cpus: cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + timebase-frequency = <25000000>; >>> + >>> + cpu0: cpu@0 { >>> + compatible = "thead,c906", "riscv"; >>> + device_type = "cpu"; >>> + reg = <0>; >>> + d-cache-block-size = <64>; >>> + d-cache-sets = <512>; >>> + d-cache-size = <65536>; >>> + i-cache-block-size = <64>; >>> + i-cache-sets = <128>; >>> + i-cache-size = <32768>; >>> + mmu-type = "riscv,sv39"; >>> + riscv,isa = "rv64imafdc"; >>> + riscv,isa-base = "rv64i"; >>> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >>> +        "zifencei", "zihpm"; >>> + >>> + cpu0_intc: interrupt-controller { >>> + compatible = "riscv,cpu-intc"; >>> + interrupt-controller; >>> + #interrupt-cells = <1>; >>> + }; >>>   }; >>>   }; >>>  }; >> >> Make all soc definition include the common cpu file. >> Not just copy it. > > I was acting according to Krzysztof's suggestion: > https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/ > > Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt > controllers into it. Would it make sense? I don't understand the original suggestion. Inochi, please trim unnecessary context from replies. Best regards, Krzysztof