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Mon, 13 Jul 2026 16:43:46 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 13 Jul 2026 16:43:45 +0800 Message-ID: <33e6094d-e433-4406-8fef-0feff8f05bcb@huawei.com> Date: Mon, 13 Jul 2026 16:43:44 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 14/36] arm64: interrupts: introduce generic interrupt masking helpers To: Vladimir Murzin , References: <20260709121333.23507-1-vladimir.murzin@arm.com> <20260709121333.23507-15-vladimir.murzin@arm.com> From: Jinjie Ruan In-Reply-To: <20260709121333.23507-15-vladimir.murzin@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To dggpemf500011.china.huawei.com (7.185.36.131) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260713_014358_529972_8E39FF53 X-CRM114-Status: GOOD ( 24.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, maz@kernel.org, will@kernel.org, catalin.marinas@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/9/2026 8:13 PM, Vladimir Murzin wrote: > From: Ada Couprie Diaz > > As for the entry code, we want to replace `local_daif_...` helpers > so that they can properly handle both DAIF and PMR, as well controlling > their use more strongly. > > Introduce new `local_all_irqs_...` helpers to replace them, which should > only be called in save/restore pairs. > > Save the requested interrupt state as well, so we can check for > inconsistent interrupt masking in between save and restore. > > There are two exceptions where it does not make sense to force > save/restore pairs for modifying the interrupt masks: > - when initializing a CPU or > - preparing to turn it off. > > As we otherwise want to force save/restore pairs, those cases are > handled with specific helpers, making clear that they should not be > used outside of those cases, enforced with `CONFIG_DEBUG_IRQFLAGS` > enabled. > > Signed-off-by: Ada Couprie Diaz > Signed-off-by: Vladimir Murzin > --- > arch/arm64/include/asm/interrupts/masking.h | 101 ++++++++++++++++++++ > 1 file changed, 101 insertions(+) > create mode 100644 arch/arm64/include/asm/interrupts/masking.h > > diff --git a/arch/arm64/include/asm/interrupts/masking.h b/arch/arm64/include/asm/interrupts/masking.h > new file mode 100644 > index 000000000000..66ee03f7ab68 > --- /dev/null > +++ b/arch/arm64/include/asm/interrupts/masking.h > @@ -0,0 +1,101 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2025 Arm Ltd. > + */ > +#ifndef __ASM_INTERRUPTS_MASKING_H > +#define __ASM_INTERRUPTS_MASKING_H > + > +#include > +#include > +#include > +#include > +#include > + > +typedef struct arm64_exc_hwstates { > + arm64_exc_hwstate_t saved; > + arm64_exc_hwstate_t expected; > +} arm64_exc_hwstates_t; > + > +#ifdef CONFIG_DEBUG_IRQFLAGS > +/* Make sure the CPU init/tear down masking functions are only used once. */ > +static DEFINE_PER_CPU(bool, irqs_masks_cpu_init_done); > +static DEFINE_PER_CPU(bool, irqs_masks_cpu_final_done); > +#endif > + > +static inline > +arm64_exc_hwstates_t local_all_irqs_save_mask(arm64_exc_context_t new) I think the name "all irqs" is inappropriate, because it also masks DEBUG exceptions and SERROR exceptions, which are not irqs. Maybe local_exceptions_save_mask()? > +{ > + arm64_exc_hwstate_t state = arm64_exc_hwstate_of_context(new); > + arm64_exc_hwstate_t actual = {.flags = arch_local_save_flags()}; > + > + if (IS_ENABLED(CONFIG_DEBUG_IRQFLAGS)) { > + bool pnmi = system_uses_irq_prio_masking(); > + > + WARN_ON_ONCE(new < CRITICAL_CONTEXT && > + actual.daif == DAIF_MASK); > + > + WARN_ON_ONCE(new < ERROR_CONTEXT && > + actual.daif == DAIF_ERRCTX); > + > + WARN_ON_ONCE(new < NONMI_CONTEXT && > + pnmi && actual.daif == DAIF_PROCCTX_NOIRQ); > + > + WARN_ON_ONCE(new < NOIRQ_CONTEXT && > + ((pnmi && actual.pmr == GIC_PRIO_IRQOFF) || > + (!pnmi && actual.daif == DAIF_PROCCTX_NOIRQ))); > + } > + > + arm64_update_exc_hwstate(state, actual.pmr != state.pmr); > + > + if (!arch_irqs_disabled_flags(actual.flags)) > + trace_hardirqs_off(); > + > + return (arm64_exc_hwstates_t){.saved = actual, .expected = state}; > +} > + > +static inline void local_all_irqs_restore(arm64_exc_hwstates_t states) > +{ > + arm64_debug_exc_hwstate(states.expected); > + > + if (!arch_irqs_disabled_flags(states.saved.flags)) > + trace_hardirqs_on(); > + > + arm64_update_exc_hwstate(states.saved, true); > +} > + > +#ifdef CONFIG_DEBUG_IRQFLAGS > +static inline > +void local_all_irqs_cpu_init_mask(arm64_exc_context_t context) > +{ > + WARN_ON(__this_cpu_read(irqs_masks_cpu_init_done)); > + if (context == PROCESS_CONTEXT) > + trace_hardirqs_on(); > + arm64_update_exc_context(context, true); > + __this_cpu_write(irqs_masks_cpu_init_done, true); > + __this_cpu_write(irqs_masks_cpu_final_done, false); > +} > + > +static inline void local_all_irqs_final_mask(void) > +{ > + WARN_ON(__this_cpu_read(irqs_masks_cpu_final_done)); > + arm64_update_exc_context(CRITICAL_CONTEXT, true); > + trace_hardirqs_off(); > + __this_cpu_write(irqs_masks_cpu_final_done, true); > + __this_cpu_write(irqs_masks_cpu_init_done, false); > +} > +#else /* CONFIG_DEBUG_IRQFLAGS */ > +static inline > +void local_all_irqs_cpu_init_mask(arm64_exc_context_t context) > +{ > + if (context == PROCESS_CONTEXT) > + trace_hardirqs_on(); > + arm64_update_exc_context(context, true); > +} > + > +static inline void local_all_irqs_final_mask(void) > +{ > + arm64_update_exc_context(CRITICAL_CONTEXT, true); > + trace_hardirqs_off(); > +} > +#endif /* CONFIG_DEBUG_IRQFLAGS */ > +#endif /* __ASM_INTERRUPTS_MASKING_H */