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Tue, 9 Apr 2019 02:56:09 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 9 Apr 2019 02:56:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 9 Apr 2019 02:56:09 -0500 Received: from [172.24.190.89] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x397u5ad064157; Tue, 9 Apr 2019 02:56:06 -0500 Subject: Re: [PATCH 1/2] dt-bindings: clock: Add binding documentation for TI syscon gate clock To: Rob Herring References: <20190312090518.28666-1-vigneshr@ti.com> <20190312090518.28666-2-vigneshr@ti.com> <20190328123142.GA6229@bogus> From: Vignesh Raghavendra Message-ID: <33f6bc53-a361-c12b-1c21-3c34b101e67a@ti.com> Date: Tue, 9 Apr 2019 13:27:04 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190328123142.GA6229@bogus> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190409_005612_952951_06F1CEDD X-CRM114-Status: GOOD ( 19.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Menon, Nishanth" , "devicetree@vger.kernel.org" , Stephen Boyd , Michael Turquette , "linux-kernel@vger.kernel.org" , "Kristo, Tero" , Santosh Shilimkar , "linux-clk@vger.kernel.org" , Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On 28/03/19 6:01 PM, Rob Herring wrote: > On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote: >> Add dt bindings for TI syscon gate clock. >> >> Signed-off-by: Vignesh Raghavendra >> --- >> .../bindings/clock/ti,syscon-gate-clock.txt | 35 +++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt b/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt >> new file mode 100644 >> index 000000000000..f2bc4281ddba >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt >> @@ -0,0 +1,35 @@ >> +TI syscon gate clock >> + >> +The gate clock node must be provided inside a system controller node. >> + >> +Required: >> +- comaptible: Must be "ti,syscon-gate-clock" >> +- reg: Offset of register that controls the clock within syscon regmap >> +- ti,clock-bit-idx: bit index that control gate/ungating of clock >> +- clocks: phandle to the clock parent >> +- #clock-cells: must be <0> >> + >> +Example: >> + ctrlmmr_epwm_ctrl: syscon@104140{ >> + compatible = "syscon", "simple-bus"; > > Can't be both of these... > These registers have bits that control other functionalities apart from PWM clocks. Therefore, I modeled them as "syscon", "simple-bus"; Or is it recommended to use: compatible = "syscon", "simple-mfd"; >> + reg = <0x0 0x104140 0x0 0x18>; >> + ranges = <0x0 0x0 0x104140>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + ehrpwm0_tbclk: clk@0 { >> + compatible = "ti,syscon-gate-clock"; >> + reg = <0x0>; >> + #clock-cells = <0>; >> + clocks = <&k3_clks 40 0>; >> + ti,clock-bit-idx = <0>; > > This would imply you have multiple nodes at one address which is > discouraged. > >> + }; > > We generally don't describe clocks as 1 clock per node. Give the parent > a specific compatible and make it a clock provider. > Ok, I can change this to single clock node and use #clock-cells to pass register offset of and bit index from each consumer: ctrlmmr_epwm_ctrl: syscon@104140{ compatible = "syscon", "simple-mfd"; reg = <0x0 0x104140 0x0 0x18>; ranges = <0x0 0x0 0x104140>; #address-cells = <1>; #size-cells = <0>; ehrpwm_tbclk: clk { compatible = "ti,syscon-gate-clock"; #clock-cells = <2>; }; }; And consumer node: ehrpwm1: pwm@3010000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x0 0x3000000 0x0 0x100>; power-domains = <&k3_pds 40>; clocks = <&ehrpwm_tbclk 4 0>; /* offset 4, bit 0 */ clock-names = "tbclk"; }; Would that be acceptable? Regards Vignesh >> + >> + ehrpwm1_tbclk: clk@4 { >> + compatible = "ti,syscon-gate-clock"; >> + reg = <0x4>; >> + #clock-cells = <0>; >> + clocks = <&k3_clks 41 0>; >> + ti,clock-bit-idx = <0>; >> + }; >> + }; >> -- >> 2.21.0 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel