Re: [PATCH v1 1/1] arm64: dts: imx8qm-ss-dma: add LPUART4

[Alexander Stein <alexander.stein@ew.tq-group.com>]

Hi Stefano,

Am Mittwoch, 22. Juli 2026, 12:42:00 CEST schrieb Stefano Radaelli:
> From: Stefano Radaelli <stefano.r@variscite.com>
> 
> Add the missing LPUART4 node to the i.MX8QM DMA subsystem description.
> 
> The peripheral is present in the SoC and its LPCG clock controller is
> already described, but the UART device node is currently missing.
> Describe its registers, interrupt, clocks, power domain and eDMA
> channels based on the NXP downstream device tree.
> 
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>

Commit d879cc948e6f7 ("arm64: dts: imx8qm-ss-dma: add lpuart4 node") landed
in next-20260721, which is essentially the same patch.

Best regards,
Alexander

> ---
>  arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> index 974e193f8dcb..25c5e4423163 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> @@ -8,6 +8,22 @@
>  /delete-node/ &adma_pwm_lpcg;
>  
>  &dma_subsys {
> +	lpuart4: serial@5a0a0000 {
> +		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
> +		reg = <0x5a0a0000 0x1000>;
> +		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gic>;
> +		clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>;
> +		clock-names = "ipg", "baud";
> +		assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <80000000>;
> +		power-domains = <&pd IMX_SC_R_UART_4>;
> +		dma-names = "rx","tx";
> +		dmas = <&edma2 20 0 1>,
> +		       <&edma2 21 0 0>;
> +		status = "disabled";
> +	};
> +
>  	uart4_lpcg: clock-controller@5a4a0000 {
>  		compatible = "fsl,imx8qxp-lpcg";
>  		reg = <0x5a4a0000 0x10000>;
> 


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