From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC4D2C4CEC6 for ; Thu, 12 Sep 2019 14:03:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7EEED20CC7 for ; Thu, 12 Sep 2019 14:03:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Go2ry7I2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7EEED20CC7 Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1i8PgR-0008TV-BY; Thu, 12 Sep 2019 14:02:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1i8PgN-0008TB-Cj for linux-arm-kernel@lists.infradead.org; Thu, 12 Sep 2019 14:02:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B05D828; Thu, 12 Sep 2019 07:02:46 -0700 (PDT) Received: from [10.249.163.245] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B8E8A3F71F; Thu, 12 Sep 2019 07:02:44 -0700 (PDT) Subject: Re: [PATCH v5 2/3] dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu To: andrew.murray@arm.com, mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com References: <20190816154615.39854-1-andrew.murray@arm.com> <20190816154615.39854-3-andrew.murray@arm.com> From: Suzuki K Poulose Message-ID: <34570d2f-b9b7-a45e-8a52-86808198755b@arm.com> Date: Thu, 12 Sep 2019 15:06:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20190816154615.39854-3-andrew.murray@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190912_070247_478335_20CF6DD5 X-CRM114-Status: GOOD ( 19.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Al.Grant@arm.com, coresight@lists.linaro.org, leo.yan@linaro.org, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08/16/2019 04:46 PM, Andrew Murray wrote: > Some coresight components, because of choices made during hardware > integration, require their state to be saved and restored across CPU low > power states. > > The software has no reliable method of detecting when save/restore is > required thus let's add a binding to inform the kernel. > > Signed-off-by: Andrew Murray > --- > Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index fcc3bacfd8bc..d02c42d21f2f 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -87,6 +87,15 @@ its hardware characteristcs. > > * port or ports: see "Graph bindings for Coresight" below. > > +* Optional properties for all components: > + > + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the > + hardware will lose register context on CPU power down (e.g. CPUIdle). > + An example of where this may be needed are systems which contain a > + coresight component and CPU in the same power domain. When the CPU > + powers down the coresight component also powers down and loses its > + context. This property is currently only used for the ETM 4.x driver. > + > * Optional properties for ETM/PTMs: > > * arm,cp14: must be present if the system accesses ETM/PTM management > Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel