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From: Dinh Nguyen <dinguyen@kernel.org>
To: "Nazle Asmade,
	Muhammad Nazim Amirul"
	<muhammad.nazim.amirul.nazle.asmade@altera.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: "maxime.chevallier@bootlin.com" <maxime.chevallier@bootlin.com>,
	"rmk+kernel@armlinux.org.uk" <rmk+kernel@armlinux.org.uk>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	"andrew+netdev@lunn.ch" <andrew+netdev@lunn.ch>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v4 4/4] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter
Date: Tue, 11 Aug 2026 10:34:22 -0500	[thread overview]
Message-ID: <351d66fd-d904-4305-814c-0c3bda2361c4@kernel.org> (raw)
In-Reply-To: <e3c2a7c5-35d3-4c40-9adb-39e9c8659af8@altera.com>



On 7/26/26 21:07, Nazle Asmade, Muhammad Nazim Amirul wrote:
> On 16/7/2026 3:56 pm, Krzysztof Kozlowski wrote:
>> On Wed, Jul 15, 2026 at 07:19:32PM -0700, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>>
>>> The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter
>>> implemented as FPGA soft IP between gmac1 and its PHY. This converter
>>> provides the RGMII TX/RX clock delays, so the MAC interface selector
>>> must be configured for GMII while the PHY is configured without delays.
>>>
>>> Add the "altr,socfpga-stmmac-agilex5-tsn" compatible to the match table
>>> and detect it in probe to force GMII for the MAC interface selector and
>>> strip the delay bits from phy_interface so the PHY is not configured to
>>> add delays already provided by the FPGA converter.
>>>
>>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>>> ---
>>> v4: Add Reviewed-by from Andrew Lunn.
>>>
>>>    drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 ++++++++++++-
>>>    1 file changed, 12 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> index 1d7f0a57d288..bf591a68502f 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
>>> @@ -69,12 +69,13 @@ struct socfpga_dwmac {
>>>    	void __iomem *tse_pcs_base;
>>>    	void __iomem *sgmii_adapter_base;
>>>    	bool f2h_ptp_ref_clk;
>>> +	phy_interface_t mac_interface;
>>>    	const struct socfpga_dwmac_ops *ops;
>>>    };
>>>    
>>>    static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
>>>    {
>>> -	return dwmac->plat_dat->phy_interface;
>>> +	return dwmac->mac_interface;
>>>    }
>>>    
>>>    static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
>>> @@ -650,6 +651,15 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
>>>    	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
>>>    	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
>>>    
>>> +	dwmac->mac_interface = plat_dat->phy_interface;
>>> +
>>> +	if (of_device_is_compatible(pdev->dev.of_node,
>>> +				    "altr,socfpga-stmmac-agilex5-tsn")) {
>>
>> Don't add compatibles around the code. Does not scale. You have driver
>> match data exactly for that purpose.
>>
>>> +		dwmac->mac_interface = PHY_INTERFACE_MODE_GMII;
>>> +		if (phy_interface_mode_is_rgmii(plat_dat->phy_interface))
>>> +			plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;
>>> +	}
>>> +
>>>    	ops->setup_plat_dat(dwmac);
>>>    
>>>    	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
>>> @@ -674,6 +684,7 @@ static const struct of_device_id socfpga_dwmac_match[] = {
>>>    	{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
>>>    	{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
>>>    	{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
>>> +	{ .compatible = "altr,socfpga-stmmac-agilex5-tsn", .data = &socfpga_agilex5_ops },
>>
>> Otherwise dvices are compatible? They why would you need this entry in
>> the first place?
> Hi Krzysztof,
> 
> Just to confirm: should we add a separate socfpga_agilex5_tsn_ops and
> use that as .data for the TSN compatible, instead of checking the
> compatible string in probe and reusing socfpga_agilex5_ops?
> 
>
I believe that is right way to do it instead of looking for compatibles 
around code.


Dinh


      reply	other threads:[~2026-08-11 15:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-16  2:19 [PATCH v4 0/4] Add Agilex5 SoCDK TSN Config2 board support muhammad.nazim.amirul.nazle.asmade
2026-07-16  2:19 ` [PATCH v4 1/4] dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board muhammad.nazim.amirul.nazle.asmade
2026-07-16  2:19 ` [PATCH v4 2/4] arm64: dts: socfpga: agilex5: Add " muhammad.nazim.amirul.nazle.asmade
2026-07-16  2:19 ` [PATCH v4 3/4] dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible muhammad.nazim.amirul.nazle.asmade
2026-07-16  7:58   ` Krzysztof Kozlowski
2026-07-27  2:08     ` Nazle Asmade, Muhammad Nazim Amirul
2026-07-16  2:19 ` [PATCH net-next v4 4/4] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter muhammad.nazim.amirul.nazle.asmade
2026-07-16  7:56   ` Krzysztof Kozlowski
2026-07-27  2:07     ` Nazle Asmade, Muhammad Nazim Amirul
2026-08-11 15:34       ` Dinh Nguyen [this message]

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