From: tomasz.figa@gmail.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider
Date: Fri, 23 Aug 2013 22:02:40 +0200 [thread overview]
Message-ID: <3550203.JkdqaguvYB@flatron> (raw)
In-Reply-To: <1377241078-11808-6-git-send-email-rahul.sharma@samsung.com>
Hi Rahul,
On Friday 23 of August 2013 12:27:58 Rahul Sharma wrote:
> sclk_pixel is used to represent pixel clock divider on all exynos
> SoCs not as a gate clock. It is queried in driver to pass as the
> parent to hdmi clock while switching between parents. A new ID can
> be asssigned Pixel gate clock which is currently not in use. Pixel
> clock gate is default 'on'.
This doesn't sound like a correct assumption, especially if you recall how
common clock framework works - it disables any unclaimed clock
automatically. Also we might want to support gating from power management
reasons.
IMHO you should simply export the dout_hdmi_pixel clock, keeping the
original sclk_pixel exported as well.
Best regards,
Tomasz
next prev parent reply other threads:[~2013-08-23 20:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-23 6:57 [PATCH v2 0/5] clk/exynos5420: add clocks for hdmi subsystem Rahul Sharma
2013-08-23 6:57 ` [PATCH v2 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks Rahul Sharma
2013-08-23 6:57 ` [PATCH v2 2/5] clk/exynos5420: add gate clock for mixer sysmmu Rahul Sharma
2013-08-23 6:57 ` [PATCH v2 3/5] clk/exynos5420: fix the order of parents of hdmi mux Rahul Sharma
2013-08-23 6:57 ` [PATCH v2 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver Rahul Sharma
2013-08-23 6:57 ` [PATCH v2 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider Rahul Sharma
2013-08-23 20:02 ` Tomasz Figa [this message]
2013-08-24 6:39 ` Rahul Sharma
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