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Thu, 4 Sep 2025 01:22:21 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 01:22:21 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 01:22:21 -0500 Received: from [172.24.20.139] (lt5cd2489kgj.dhcp.ti.com [172.24.20.139]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5846MG4d2521411; Thu, 4 Sep 2025 01:22:16 -0500 Message-ID: <35cc8bec-dd7b-48b6-b2e8-c53c82231a58@ti.com> Date: Thu, 4 Sep 2025 11:52:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register To: Harikrishna Shenoy , , , , , , , , , , , , , , , , References: <20250904050940.2913567-1-h-shenoy@ti.com> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <20250904050940.2913567-1-h-shenoy@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250903_232235_643952_0C5AF561 X-CRM114-Status: GOOD ( 13.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/4/2025 10:39 AM, Harikrishna Shenoy wrote: > Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in > TRM Table 2-1 MAIN Domain Memory Map. > Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM > > Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY") > > Signed-off-by: Harikrishna Shenoy > --- > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index ab3666ff4297..3fa7537d5414 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 { > * the PHY driver. > */ > reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ > - <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ > + <0x00 0x04f40000 0x00 0x100>; /* DSS_EDP0_INTG_CFG_VP */ Thanks for catching this I think other SOC "arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi" needs similar Fix > reg-names = "mhdptx", "j721e-intg"; > > clocks = <&k3_clks 151 36>;