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Mon, 11 May 2020 09:00:35 +0000 From: To: , Subject: Re: [PATCH v4 00/16] mtd: spi-nor: add xSPI Octal DTR support Thread-Topic: [PATCH v4 00/16] mtd: spi-nor: add xSPI Octal DTR support Thread-Index: AQHWJ3Khn/aolf/mv0usqjltSIxTLg== Date: Mon, 11 May 2020 09:00:35 +0000 Message-ID: <3649933.zuh8VGJVCz@192.168.0.120> References: <20200424184410.8578-1-p.yadav@ti.com> In-Reply-To: <20200424184410.8578-1-p.yadav@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: ti.com; dkim=none (message not signed) header.d=none;ti.com; dmarc=none action=none header.from=microchip.com; x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 92a278c0-aece-4143-0505-08d7f589c47d x-ms-traffictypediagnostic: BY5PR11MB3975: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 04004D94E2 x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexandre.belloni@bootlin.com, vigneshr@ti.com, richard@nod.at, nsekhar@ti.com, linux-kernel@vger.kernel.org, Ludovic.Desroches@microchip.com, broonie@kernel.org, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Pratyush, Boris, On Friday, April 24, 2020 9:43:54 PM EEST Pratyush Yadav wrote: > This series adds support for octal DTR flashes in the spi-nor framework, I'm still learning about this, but I can give you my 2 cents as of now, to open the discussion. Enabling 2-2-2, 4-4-4, and 8-8-8 modes is dangerous because the flash may not recover from unexpected resets. Entering one of these modes can be: 1/ volatile selectable, the device return to the 1-1-1 protocol after the next power-on. I guess this is conditioned by the optional RESET pin, but I'll have to check. Also the flash can return to the 1-1-1 mode using the software reset or through writing to its Configuration Register, without power-on or power- off. 2/ non-volatile selectable in which RESET# and software reset are useless, the flash defaults to the mode selected in the non volatile Configuration Register bits. The only way to get back to 1-1-1 is to write to the Configuration Register. Not recovering from unexpected resets is unacceptable. One should always prefer option 1/ and condition the entering in 2-2-2, 4-4-4 and 8-8-8 with the presence of the optional RESET pin. For the unfortunate flashes that support just option 2/, we should not enter these modes on our own, just by discovering the capabilities from the SFDP tables or by the flags in the flash_info struct. The best we can do for them is to move the responsibility to the user. Maybe to add a Kconfig option that is disabled by default with which we condition the entering in 2-2-2, 4-4-4 or 8-8-8 modes. Once entered in one of these modes, if an unexpected reset comes, you most likely are doomed, because early stage bootloaders may not work in these modes and you'll not be able to boot the board. Assuming that one uses other environment to boot the board, we should at least make sure that the flash works in linux after an unexpected reset. We should try to determine in which mode we are at init, so maybe an extension of the default_init hook is needed. But all this looks like a BIG compromise, I'm not yet sure if we should adress 2/. Thoughts? I'm still looking into this. Cheers, ta _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel