From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Mon, 16 Mar 2015 21:00:42 +0100 Subject: [PATCH v2 4/5] PCI: designware: Add disable IO support In-Reply-To: <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> Message-ID: <3714853.Vuc23EfWdL@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday 16 March 2015 13:00:51 Kumar Gala wrote: > On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: > > > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > > But in these SoCs PCIe IP doesn't support IO. > > > > This patch adds the possibility to disable it through > > a DT property, by creating an empty IO window and by > > removing PCI_COMMAND_IO from the setup register. > > > > Signed-off-by: Fabrice Gasnier > > Signed-off-by: Gabriel Fernandez > > --- > > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ > > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- > > drivers/pci/host/pcie-designware.h | 1 + > > 3 files changed, 25 insertions(+), 2 deletions(-) > > Why not just update the code such that if the ranges doesn?t have an IO > space rather than introducing a new DT property? I suspect we can simplify this now by changing over the designware PCI code from pci_common_init_dev to calling pci_scan_root_bus() in the same way that pci-versatile.c does. This would also clean up some other areas of the driver and let you do proper error handling in the probe. Arnd