* Re: [PATCH v2 2/2] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576 [not found] ` <20240808170113.82775-3-detlev.casanova@collabora.com> @ 2024-08-09 13:16 ` Heiko Stübner 0 siblings, 0 replies; 3+ messages in thread From: Heiko Stübner @ 2024-08-09 13:16 UTC (permalink / raw) To: linux-kernel, Detlev Casanova Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Jose Abreu, Maxime Coquelin, David Wu, Giuseppe Cavallaro, netdev, devicetree, linux-arm-kernel, linux-rockchip, linux-stm32, kernel, Detlev Casanova Hi Detlev, Am Donnerstag, 8. August 2024, 19:00:18 CEST schrieb Detlev Casanova: > From: David Wu <david.wu@rock-chips.com> > > Add constants and callback functions for the dwmac on RK3576 soc. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > [rebase, extracted bindings] > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > --- > .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 156 ++++++++++++++++++ > 1 file changed, 156 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > index 7ae04d8d291c8..e1fa8fc9f4012 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > @@ -1116,6 +1116,161 @@ static const struct rk_gmac_ops rk3568_ops = { > }, > }; > > +/* VCCIO0_1_3_IOC */ > +#define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 > +#define RK3576_VCCIO0_1_3_IOC_CON3 0X640c > +#define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 > +#define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 > + > +#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) > +#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) > +#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) > +#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) > + > +#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) > +#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) > + > +/* SDGMAC_GRF */ > +#define RK3576_GRF_GMAC_CON0 0X0020 > +#define RK3576_GRF_GMAC_CON1 0X0024 > + > +#define RK3576_GMAC_RMII_MODE GRF_BIT(3) > +#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) > + > +#define RK3576_GMAC_CLK_SELET_IO GRF_BIT(7) > +#define RK3576_GMAC_CLK_SELET_CRU GRF_CLR_BIT(7) nit: typos _CLK_SELECT_ ... missing the C in select > + > +#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) > +#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) I think those are backwards The TRM says bit[5]=0: 25MHz (DIV2) and bit[5]=1: 2.5MHz (DIV20) I guess nobody also on Rockchip's side tested a RMII phy on those controllrs > + > +#define RK3576_GMAC_CLK_RGMII_DIV1 \ > + (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) > +#define RK3576_GMAC_CLK_RGMII_DIV5 \ > + (GRF_BIT(6) | GRF_BIT(5)) > +#define RK3576_GMAC_CLK_RGMII_DIV50 \ > + (GRF_BIT(6) | GRF_CLR_BIT(5)) > + in contrast, these are correct and match the TRM > +#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) > +#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) > + > +static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, > + int tx_delay, int rx_delay) > +{ > + struct device *dev = &bsp_priv->pdev->dev; > + unsigned int offset_con; > + > + if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { > + dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); > + return; > + } > + > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > + RK3576_GRF_GMAC_CON0; > + > + regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); > + > + offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : > + RK3576_VCCIO0_1_3_IOC_CON2; > + > + /* m0 && m1 delay enabled */ > + regmap_write(bsp_priv->php_grf, offset_con, > + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); > + regmap_write(bsp_priv->php_grf, offset_con + 0x4, > + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); > + > + /* m0 && m1 delay value */ > + regmap_write(bsp_priv->php_grf, offset_con, > + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | > + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); > + regmap_write(bsp_priv->php_grf, offset_con + 0x4, > + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | > + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); > +} > + > +static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) > +{ > + struct device *dev = &bsp_priv->pdev->dev; > + unsigned int offset_con; > + > + if (IS_ERR(bsp_priv->php_grf)) { > + dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__); > + return; > + } > + > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > + RK3576_GRF_GMAC_CON0; > + > + regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); > +} > + > +static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) > +{ > + struct device *dev = &bsp_priv->pdev->dev; > + unsigned int val = 0, offset_con; > + > + switch (speed) { > + case 10: > + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) > + val = RK3576_GMAC_CLK_RMII_DIV20; > + else > + val = RK3576_GMAC_CLK_RGMII_DIV50; val = bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII ? RK3576_GMAC_CLK_RMII_DIV20 : RK3576_GMAC_CLK_RGMII_DIV50; perhaps? > + break; > + case 100: > + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) > + val = RK3576_GMAC_CLK_RMII_DIV2; > + else > + val = RK3576_GMAC_CLK_RGMII_DIV5; same as above? > + break; > + case 1000: > + if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) > + val = RK3576_GMAC_CLK_RGMII_DIV1; > + else > + goto err; if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) goto err; val = RK3576_GMAC_CLK_RGMII_DIV1; > + break; > + default: > + goto err; > + } > + > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > + RK3576_GRF_GMAC_CON0; > + > + regmap_write(bsp_priv->grf, offset_con, val); > + > + return; > +err: > + dev_err(dev, "unknown speed value for GMAC speed=%d", speed); > +} > + > +static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, > + bool enable) > +{ > + unsigned int val = input ? RK3576_GMAC_CLK_SELET_IO : > + RK3576_GMAC_CLK_SELET_CRU; > + unsigned int offset_con; > + > + val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : > + RK3576_GMAC_CLK_RMII_GATE; > + > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > + RK3576_GRF_GMAC_CON0; nit: alignment of both looks like it could be nicer Heiko ^ permalink raw reply [flat|nested] 3+ messages in thread
[parent not found: <3304458.aeNJFYEL58@trenzalore>]
[parent not found: <a73ff2ab-7e68-4d6b-b38d-37e7303af40d@rock-chips.com>]
* Re: [PATCH v2 2/2] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576 [not found] ` <a73ff2ab-7e68-4d6b-b38d-37e7303af40d@rock-chips.com> @ 2024-08-15 16:35 ` Heiko Stübner 0 siblings, 0 replies; 3+ messages in thread From: Heiko Stübner @ 2024-08-15 16:35 UTC (permalink / raw) To: Detlev Casanova, linux-kernel, David Wu Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Jose Abreu, Maxime Coquelin, Giuseppe Cavallaro, netdev, devicetree, linux-arm-kernel, linux-rockchip, linux-stm32, kernel Hi David, Am Montag, 12. August 2024, 04:21:27 CEST schrieb David Wu: > Hi Detlev, Heiko: > > It's really a TRM error here, RMII PHY has been verified for this patch. thanks for double checking. Heiko > 在 2024/8/9 22:38, Detlev Casanova 写道: > > Can't be sure about that. An error in the TRM is not impossible either, as for > > rk3588, it is also bit[5]=0: DIV20 and bit[5]=1: DIV2. I can switch them to > > match the TRM though, we may never now. ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2 2/2] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576 [not found] ` <3304458.aeNJFYEL58@trenzalore> [not found] ` <a73ff2ab-7e68-4d6b-b38d-37e7303af40d@rock-chips.com> @ 2024-08-15 16:37 ` Heiko Stübner 1 sibling, 0 replies; 3+ messages in thread From: Heiko Stübner @ 2024-08-15 16:37 UTC (permalink / raw) To: linux-kernel, Detlev Casanova Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Jose Abreu, Maxime Coquelin, David Wu, Giuseppe Cavallaro, netdev, devicetree, linux-arm-kernel, linux-rockchip, linux-stm32, kernel Am Freitag, 9. August 2024, 16:38:23 CEST schrieb Detlev Casanova: > On Friday, 9 August 2024 09:16:44 EDT Heiko Stübner wrote: > > Hi Detlev, > > > > Am Donnerstag, 8. August 2024, 19:00:18 CEST schrieb Detlev Casanova: > > > From: David Wu <david.wu@rock-chips.com> > > > > > > Add constants and callback functions for the dwmac on RK3576 soc. > > > > > > Signed-off-by: David Wu <david.wu@rock-chips.com> > > > [rebase, extracted bindings] > > > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > > > --- > > > > > > .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 156 ++++++++++++++++++ > > > 1 file changed, 156 insertions(+) > > > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > > > b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index > > > 7ae04d8d291c8..e1fa8fc9f4012 100644 > > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > > > @@ -1116,6 +1116,161 @@ static const struct rk_gmac_ops rk3568_ops = { > > > > > > }, > > > > > > }; > > > > > [...] > > > > +/* SDGMAC_GRF */ > > > +#define RK3576_GRF_GMAC_CON0 0X0020 > > > +#define RK3576_GRF_GMAC_CON1 0X0024 > > > + > > > +#define RK3576_GMAC_RMII_MODE GRF_BIT(3) > > > +#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) > > > + > > > +#define RK3576_GMAC_CLK_SELET_IO GRF_BIT(7) > > > +#define RK3576_GMAC_CLK_SELET_CRU GRF_CLR_BIT(7) > > > > nit: typos _CLK_SELECT_ ... missing the C in select > > Ack So all points below are resolved, and with the C added Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > > > + > > > +#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) > > > +#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) > > > > I think those are backwards > > The TRM says bit[5]=0: 25MHz (DIV2) and bit[5]=1: 2.5MHz (DIV20) > > > > I guess nobody also on Rockchip's side tested a RMII phy on those controllrs > > Can't be sure about that. An error in the TRM is not impossible either, as for > rk3588, it is also bit[5]=0: DIV20 and bit[5]=1: DIV2. I can switch them to > match the TRM though, we may never now. As David said, the TRM is wrong and the code is correct, so all good > > > > + > > > +#define RK3576_GMAC_CLK_RGMII_DIV1 \ > > > + (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) > > > +#define RK3576_GMAC_CLK_RGMII_DIV5 \ > > > + (GRF_BIT(6) | GRF_BIT(5)) > > > +#define RK3576_GMAC_CLK_RGMII_DIV50 \ > > > + (GRF_BIT(6) | GRF_CLR_BIT(5)) > > > + > > > > in contrast, these are correct and match the TRM > > > > > +#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) > > > +#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) > > > + > > > +static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, > > > + int tx_delay, int rx_delay) > > > +{ > > > + struct device *dev = &bsp_priv->pdev->dev; > > > + unsigned int offset_con; > > > + > > > + if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { > > > + dev_err(dev, "Missing rockchip,grf or rockchip,php_grf > property\n"); > > > + return; > > > + } > > > + > > > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > > > + RK3576_GRF_GMAC_CON0; > > > + > > > + regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); > > > + > > > + offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : > > > + > RK3576_VCCIO0_1_3_IOC_CON2; > > > + > > > + /* m0 && m1 delay enabled */ > > > + regmap_write(bsp_priv->php_grf, offset_con, > > > + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); > > > + regmap_write(bsp_priv->php_grf, offset_con + 0x4, > > > + DELAY_ENABLE(RK3576, tx_delay, rx_delay)); > > > + > > > + /* m0 && m1 delay value */ > > > + regmap_write(bsp_priv->php_grf, offset_con, > > > + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | > > > + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); > > > + regmap_write(bsp_priv->php_grf, offset_con + 0x4, > > > + RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | > > > + RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); > > > +} > > > + > > > +static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) > > > +{ > > > + struct device *dev = &bsp_priv->pdev->dev; > > > + unsigned int offset_con; > > > + > > > + if (IS_ERR(bsp_priv->php_grf)) { > > > + dev_err(dev, "%s: Missing rockchip,php_grf property\n", > __func__); > > > + return; > > > + } > > > + > > > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > > > + RK3576_GRF_GMAC_CON0; > > > + > > > + regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); > > > +} > > > + > > > +static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int > > > speed) +{ > > > + struct device *dev = &bsp_priv->pdev->dev; > > > + unsigned int val = 0, offset_con; > > > + > > > + switch (speed) { > > > + case 10: > > > + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) > > > + val = RK3576_GMAC_CLK_RMII_DIV20; > > > + else > > > + val = RK3576_GMAC_CLK_RGMII_DIV50; > > > > val = bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII ? > > RK3576_GMAC_CLK_RMII_DIV20 : > > RK3576_GMAC_CLK_RGMII_DIV50; > > perhaps? > > This way matches how it is written in rk3588_set_gmac_speed(). I find that > having similar code for similar functions helps reading and understanding it > better (although I agree that your suggestion looks better). > > I'd rather keep it like it is for now if that's ok. ok, there is not much difference between the two variants anyway. > > > + break; > > > + case 100: > > > + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) > > > + val = RK3576_GMAC_CLK_RMII_DIV2; > > > + else > > > + val = RK3576_GMAC_CLK_RGMII_DIV5; > > > > same as above? > > > > > + break; > > > + case 1000: > > > + if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) > > > + val = RK3576_GMAC_CLK_RGMII_DIV1; > > > + else > > > + goto err; > > > > if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) > > goto err; > > > > val = RK3576_GMAC_CLK_RGMII_DIV1; > > > > > + break; > > > + default: > > > + goto err; > > > + } > > > + > > > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > > > + RK3576_GRF_GMAC_CON0; > > > + > > > + regmap_write(bsp_priv->grf, offset_con, val); > > > + > > > + return; > > > +err: > > > + dev_err(dev, "unknown speed value for GMAC speed=%d", speed); > > > +} > > > + > > > +static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, > > > bool input, + bool enable) > > > +{ > > > + unsigned int val = input ? RK3576_GMAC_CLK_SELET_IO : > > > + RK3576_GMAC_CLK_SELET_CRU; > > > + unsigned int offset_con; > > > + > > > + val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : > > > + RK3576_GMAC_CLK_RMII_GATE; > > > + > > > + offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : > > > + RK3576_GRF_GMAC_CON0; > > > > nit: alignment of both looks like it could be nicer > > That's strange, the alignments looks good in vim and git diff. It also looks > nice on the archive: https://lore.kernel.org/linux-rockchip/ > 20240808170113.82775-3-detlev.casanova@collabora.com/ ok, probably just some display artifact here :-) ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-08-15 17:46 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <20240808170113.82775-1-detlev.casanova@collabora.com>
[not found] ` <20240808170113.82775-3-detlev.casanova@collabora.com>
2024-08-09 13:16 ` [PATCH v2 2/2] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576 Heiko Stübner
[not found] ` <3304458.aeNJFYEL58@trenzalore>
[not found] ` <a73ff2ab-7e68-4d6b-b38d-37e7303af40d@rock-chips.com>
2024-08-15 16:35 ` Heiko Stübner
2024-08-15 16:37 ` Heiko Stübner
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).