* [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes
@ 2018-08-31 7:25 Heiko Stuebner
2018-08-31 8:25 ` Sandy Huang
2018-09-05 19:17 ` Heiko Stübner
0 siblings, 2 replies; 3+ messages in thread
From: Heiko Stuebner @ 2018-08-31 7:25 UTC (permalink / raw)
To: linux-arm-kernel
Add the core display subsystem and vop nodes to rk3188.
Vop0 has a fully dedicated set of pins and only vop1 needs to
do pinctrl to have display output, so also add the necessary
pinctrl entries for it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
changes in v2:
- drop default pinctrl setting
Boards may use different output signals not needing
all pins.
arch/arm/boot/dts/rk3188.dtsi | 84 +++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index aa123f93f181..ff607f11f5b0 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -56,6 +56,11 @@
};
};
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop0_out>, <&vop1_out>;
+ };
+
sram: sram at 10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x8000>;
@@ -69,6 +74,38 @@
};
};
+ vop0: vop at 1010c000 {
+ compatible = "rockchip,rk3188-vop";
+ reg = <0x1010c000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop0_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ vop1: vop at 1010e000 {
+ compatible = "rockchip,rk3188-vop";
+ reg = <0x1010e000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop1_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
timer3: timer at 2000e000 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
@@ -309,6 +348,51 @@
};
};
+ lcdc1 {
+ lcdc1_dclk: lcdc1-dclk {
+ rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ lcdc1_den: lcdc1-den {
+ rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ lcdc1_hsync: lcdc1-hsync {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ lcdc1_vsync: lcdc1-vsync {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ lcdc1_rgb24: ldcd1-rgb24 {
+ rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pwm0 {
pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
--
2.17.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes
2018-08-31 7:25 [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes Heiko Stuebner
@ 2018-08-31 8:25 ` Sandy Huang
2018-09-05 19:17 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: Sandy Huang @ 2018-08-31 8:25 UTC (permalink / raw)
To: linux-arm-kernel
? 2018/8/31 15:25, Heiko Stuebner ??:
> Add the core display subsystem and vop nodes to rk3188.
> Vop0 has a fully dedicated set of pins and only vop1 needs to
> do pinctrl to have display output, so also add the necessary
> pinctrl entries for it.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> changes in v2:
> - drop default pinctrl setting
> ?? Boards may use different output signals not needing
> ?? all pins.
>
> ? arch/arm/boot/dts/rk3188.dtsi | 84 +++++++++++++++++++++++++++++++++++
> ? 1 file changed, 84 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
> index aa123f93f181..ff607f11f5b0 100644
> --- a/arch/arm/boot/dts/rk3188.dtsi
> +++ b/arch/arm/boot/dts/rk3188.dtsi
> @@ -56,6 +56,11 @@
> ? ?? ??? ?};
> ? ?? ?};
>
> +?? ?display-subsystem {
> +?? ??? ?compatible = "rockchip,display-subsystem";
> +?? ??? ?ports = <&vop0_out>, <&vop1_out>;
> +?? ?};
> +
> ? ?? ?sram: sram at 10080000 {
> ? ?? ??? ?compatible = "mmio-sram";
> ? ?? ??? ?reg = <0x10080000 0x8000>;
> @@ -69,6 +74,38 @@
> ? ?? ??? ?};
> ? ?? ?};
>
> +?? ?vop0: vop at 1010c000 {
> +?? ??? ?compatible = "rockchip,rk3188-vop";
> +?? ??? ?reg = <0x1010c000 0x1000>;
> +?? ??? ?interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +?? ??? ?clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
> +?? ??? ?clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> +?? ??? ?resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
> +?? ??? ?reset-names = "axi", "ahb", "dclk";
> +?? ??? ?status = "disabled";
> +
> +?? ??? ?vop0_out: port {
> +?? ??? ??? ?#address-cells = <1>;
> +?? ??? ??? ?#size-cells = <0>;
> +?? ??? ?};
> +?? ?};
> +
> +?? ?vop1: vop at 1010e000 {
> +?? ??? ?compatible = "rockchip,rk3188-vop";
> +?? ??? ?reg = <0x1010e000 0x1000>;
> +?? ??? ?interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +?? ??? ?clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
> +?? ??? ?clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> +?? ??? ?resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
> +?? ??? ?reset-names = "axi", "ahb", "dclk";
> +?? ??? ?status = "disabled";
> +
> +?? ??? ?vop1_out: port {
> +?? ??? ??? ?#address-cells = <1>;
> +?? ??? ??? ?#size-cells = <0>;
> +?? ??? ?};
> +?? ?};
> +
> ? ?? ?timer3: timer at 2000e000 {
> ? ?? ??? ?compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
> ? ?? ??? ?reg = <0x2000e000 0x20>;
> @@ -309,6 +348,51 @@
> ? ?? ??? ??? ?};
> ? ?? ??? ?};
>
> +?? ??? ?lcdc1 {
> +?? ??? ??? ?lcdc1_dclk: lcdc1-dclk {
> +?? ??? ??? ??? ?rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
> +?? ??? ??? ?};
> +
> +?? ??? ??? ?lcdc1_den: lcdc1-den {
> +?? ??? ??? ??? ?rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
> +?? ??? ??? ?};
> +
> +?? ??? ??? ?lcdc1_hsync: lcdc1-hsync {
> +?? ??? ??? ??? ?rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
> +?? ??? ??? ?};
> +
> +?? ??? ??? ?lcdc1_vsync: lcdc1-vsync {
> +?? ??? ??? ??? ?rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
> +?? ??? ??? ?};
> +
> +?? ??? ??? ?lcdc1_rgb24: ldcd1-rgb24 {
> +?? ??? ??? ??? ?rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
> +?? ??? ??? ??? ??? ??? ?<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
> +?? ??? ??? ?};
> +?? ??? ?};
> +
> ? ?? ??? ?pwm0 {
> ? ?? ??? ??? ?pwm0_out: pwm0-out {
> ? ?? ??? ??? ??? ?rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
>
Reviewed-by Sandy Huang <hjc@rock-chips.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes
2018-08-31 7:25 [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes Heiko Stuebner
2018-08-31 8:25 ` Sandy Huang
@ 2018-09-05 19:17 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: Heiko Stübner @ 2018-09-05 19:17 UTC (permalink / raw)
To: linux-arm-kernel
Am Freitag, 31. August 2018, 09:25:37 CEST schrieb Heiko Stuebner:
> Add the core display subsystem and vop nodes to rk3188.
> Vop0 has a fully dedicated set of pins and only vop1 needs to
> do pinctrl to have display output, so also add the necessary
> pinctrl entries for it.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
applied for 4.20
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-08-31 7:25 [PATCH v2] ARM: dts: rockchip: add rk3188 lcd controller nodes Heiko Stuebner
2018-08-31 8:25 ` Sandy Huang
2018-09-05 19:17 ` Heiko Stübner
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