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Wed, 29 Oct 2025 03:38:45 -0500 Received: from [10.24.73.74] (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59T8cf2O3719548; Wed, 29 Oct 2025 03:38:42 -0500 Message-ID: <37f286dd4ca58fba146b8a76738085c523d4bd97.camel@ti.com> Subject: Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets From: Siddharth Vadapalli To: Bjorn Helgaas CC: kernel test robot , , , , , , , , <18255117159@163.com>, , , , , , Date: Wed, 29 Oct 2025 14:08:52 +0530 In-Reply-To: References: <20251028114746.GA1505797@bhelgaas> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1-1 MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D9:EE_|MW4PR10MB6419:EE_ X-MS-Office365-Filtering-Correlation-Id: e5103924-ea65-4acd-25a8-08de16c69494 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013|32650700017|34020700016; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 08:38:48.4346 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5103924-ea65-4acd-25a8-08de16c69494 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR10MB6419 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251029_013854_705646_4E79520B X-CRM114-Status: GOOD ( 25.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2025-10-28 at 18:13 +0530, Siddharth Vadapalli wrote: > On Tue, 2025-10-28 at 06:47 -0500, Bjorn Helgaas wrote: >=20 > Hello Bjorn, >=20 > > On Tue, Oct 28, 2025 at 10:56:33AM +0530, Siddharth Vadapalli wrote: > > > On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote: > > > > Hi Siddharth, > > > >=20 > > > > kernel test robot noticed the following build warnings: > > > >=20 > > > > [auto build test WARNING on pci/next] > > > > [also build test WARNING on pci/for-linus linus/master v6.18-rc3 ne= xt-20251027] > > > > [If your patch is applied to the wrong git tree, kindly drop us a n= ote. > > > > And when submitting patch, we suggest to use '--base' as documented= in > > > > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > > >=20 > > > > url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Va= dapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/2= 0251027-213657 > > > > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git= next > > > > patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s= -vadapalli%40ti.com > > > > patch subject: [PATCH] PCI: cadence: Enable support for applying la= ne equalization presets > > > > config: x86_64-buildonly-randconfig-002-20251028 (https://download.= 01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config) > > > > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 > > > > reproduce (this is a W=3D1 build): (https://download.01.org/0day-ci= /archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce) > > > >=20 > > > > If you fix the issue in a separate patch/commit (i.e. not just a ne= w version of > > > > the same patch/commit), kindly add following tags > > > > > Reported-by: kernel test robot > > > > > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZP= SI-lkp@intel.com/ > > > >=20 > > > > All warnings (new ones prefixed by >>): > > > >=20 > > > > drivers/pci/controller/cadence/pcie-cadence-host.c: In function = 'cdns_pcie_setup_lane_equalization_presets': > > > > > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warn= ing: this statement may fall through [-Wimplicit-fallthrough=3D] > > > > 205 | if (presets_ngts[0] !=3D PCI_EQ_RESV) { > > > > | ^ > > > > drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: = here > > > > 225 | case PCIE_SPEED_8_0GT: > > > > | ^~~~ > > >=20 > > > Fallthrough is intentional. The lane equalization presets are program= med > > > starting from the Max Supported Link speed and we fallthrough until w= e get > > > to 8.0 GT/s. > >=20 > > It's poorly documented, but use "fallthrough" here: > >=20 > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /Documentation/process/deprecated.rst?id=3Dv6.17#n200 >=20 > Thank you for pointing me to the documentation. I will update the patch > accordingly and post the v2 patch. I have posted the v2 patch at: https://lore.kernel.org/r/20251028134601.3688030-1-s-vadapalli@ti.com/ Regards, Siddharth.