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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1reekk-00000001xsS-2M8W; Mon, 26 Feb 2024 17:26:58 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1reekh-00000001xq9-0zVD for linux-arm-kernel@lists.infradead.org; Mon, 26 Feb 2024 17:26:57 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 60A43CE12B3; Mon, 26 Feb 2024 17:26:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4E91C433C7; Mon, 26 Feb 2024 17:26:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708968412; bh=fZM20Xcez0Ojd11nkMhi0j7u+poh5PptZrihnH3T3UM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=WG3HNZcAhcu4vxBNcLVRlLZlXKFqD/vgVFUU91l6+iRc4+t9Q26Ku8SL6E1JuAQ9h 8JZ1EIu6SpqKRdeQJl7W9PL/iGYn8UwgEjMrTU8EJ35AFKFQb4qe11yxIlc1IFb6Qn 8jLi+YjRvoGv820uy16dN8H0c3Z31c638U7RURxdZz8hrahsj6S+Y0s94tWJFzsFnl PSy6iCV1+BZVXD/24Cy+TeKE+/i7Uh0BmKnv53hYqEZ8WKix9lOayBLwnXiknrbORE vvQuRsaEH1WuSwHfnQId61L6UZcLEBJ4fINnbt98CsVPCcaRVKLhanIFrHaxAW1RkC VYKhBFvjNt64A== Message-ID: <38090ee4-30c2-46b3-b16d-ae0836c640ca@kernel.org> Date: Mon, 26 Feb 2024 19:26:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v3 08/10] net: ti: icssg-prueth: Add functions to configure SR1.0 packet classifier Content-Language: en-US To: Diogo Ivo , danishanwar@ti.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew@lunn.ch, dan.carpenter@linaro.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Cc: jan.kiszka@siemens.com References: <20240221152421.112324-1-diogo.ivo@siemens.com> <20240221152421.112324-9-diogo.ivo@siemens.com> From: Roger Quadros In-Reply-To: <20240221152421.112324-9-diogo.ivo@siemens.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240226_092655_689665_7B462A02 X-CRM114-Status: GOOD ( 24.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 21/02/2024 17:24, Diogo Ivo wrote: > Add the functions to configure the SR1.0 packet classifier. > > Based on the work of Roger Quadros in TI's 5.10 SDK [1]. > > [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-5.10.y > > Co-developed-by: Jan Kiszka > Signed-off-by: Jan Kiszka > Signed-off-by: Diogo Ivo > --- > Changes in v3: > - Replace local variables in icssg_class_add_mcast_sr1() > with eth_reserved_addr_base and eth_ipv4_mcast_addr_base > > .../net/ethernet/ti/icssg/icssg_classifier.c | 113 ++++++++++++++++-- > drivers/net/ethernet/ti/icssg/icssg_prueth.c | 2 +- > drivers/net/ethernet/ti/icssg/icssg_prueth.h | 6 +- > 3 files changed, 110 insertions(+), 11 deletions(-) > > diff --git a/drivers/net/ethernet/ti/icssg/icssg_classifier.c b/drivers/net/ethernet/ti/icssg/icssg_classifier.c > index 6df53ab17fbc..71b2f89ccd8e 100644 > --- a/drivers/net/ethernet/ti/icssg/icssg_classifier.c > +++ b/drivers/net/ethernet/ti/icssg/icssg_classifier.c > @@ -274,6 +274,16 @@ static void rx_class_set_or(struct regmap *miig_rt, int slice, int n, > regmap_write(miig_rt, offset, data); > } > > +static u32 rx_class_get_or(struct regmap *miig_rt, int slice, int n) > +{ > + u32 offset, val; > + > + offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN); > + regmap_read(miig_rt, offset, &val); > + > + return val; > +} > + > void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac) > { > regmap_write(miig_rt, MAC_INTERFACE_0, (u32)(mac[0] | mac[1] << 8 | > @@ -288,6 +298,26 @@ void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac) > regmap_write(miig_rt, offs[slice].mac1, (u32)(mac[4] | mac[5] << 8)); > } > > +static void icssg_class_ft1_add_mcast(struct regmap *miig_rt, int slice, > + int slot, const u8 *addr, const u8 *mask) > +{ > + int i; > + u32 val; > + > + WARN(slot >= FT1_NUM_SLOTS, "invalid slot: %d\n", slot); > + > + rx_class_ft1_set_da(miig_rt, slice, slot, addr); > + rx_class_ft1_set_da_mask(miig_rt, slice, slot, mask); > + rx_class_ft1_cfg_set_type(miig_rt, slice, slot, FT1_CFG_TYPE_EQ); > + > + /* Enable the FT1 slot in OR enable for all classifiers */ > + for (i = 0; i < ICSSG_NUM_CLASSIFIERS_IN_USE; i++) { > + val = rx_class_get_or(miig_rt, slice, i); > + val |= RX_CLASS_FT_FT1_MATCH(slot); > + rx_class_set_or(miig_rt, slice, i, val); > + } > +} > + > /* disable all RX traffic */ > void icssg_class_disable(struct regmap *miig_rt, int slice) > { > @@ -331,30 +361,95 @@ void icssg_class_disable(struct regmap *miig_rt, int slice) > regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); > } > > -void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti) > +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti, > + bool is_sr1) > { > + int num_classifiers = is_sr1 ? ICSSG_NUM_CLASSIFIERS_IN_USE : 1; > u32 data; > + int n; > > /* defaults */ > icssg_class_disable(miig_rt, slice); > > /* Setup Classifier */ > - /* match on Broadcast or MAC_PRU address */ > - data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P; > + for (n = 0; n < num_classifiers; n++) { > + /* match on Broadcast or MAC_PRU address */ > + data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P; > > - /* multicast */ > - if (allmulti) > - data |= RX_CLASS_FT_MC; > + /* multicast */ > + if (allmulti) > + data |= RX_CLASS_FT_MC; > > - rx_class_set_or(miig_rt, slice, 0, data); > + rx_class_set_or(miig_rt, slice, n, data); > > - /* set CFG1 for OR_OR_AND for classifier */ > - rx_class_sel_set_type(miig_rt, slice, 0, RX_CLASS_SEL_TYPE_OR_OR_AND); > + /* set CFG1 for OR_OR_AND for classifier */ > + rx_class_sel_set_type(miig_rt, slice, n, > + RX_CLASS_SEL_TYPE_OR_OR_AND); > + } > > /* clear CFG2 */ > regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); > } > > +void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice) > +{ > + u32 data, offset; > + int n; > + > + /* defaults */ > + icssg_class_disable(miig_rt, slice); > + > + /* Setup Classifier */ > + for (n = 0; n < ICSSG_NUM_CLASSIFIERS_IN_USE; n++) { > + /* set RAW_MASK to bypass filters */ > + offset = RX_CLASS_GATES_N_REG(slice, n); > + regmap_read(miig_rt, offset, &data); > + data |= RX_CLASS_GATES_RAW_MASK; > + regmap_write(miig_rt, offset, data); > + } > +} > + > +void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice, > + struct net_device *ndev) > +{ > + u8 mask_addr[6] = { 0, 0, 0, 0, 0, 0xff }; > + struct netdev_hw_addr *ha; > + int slot = 2; > + > + rx_class_ft1_set_start_len(miig_rt, slice, 0, 6); > + /* reserve first 2 slots for > + * 1) 01-80-C2-00-00-XX Known Service Ethernet Multicast addresses > + * 2) 01-00-5e-00-00-XX Local Network Control Block > + * (224.0.0.0 - 224.0.0.255 (224.0.0/24)) > + */ > + icssg_class_ft1_add_mcast(miig_rt, slice, 0, > + eth_reserved_addr_base, mask_addr); > + icssg_class_ft1_add_mcast(miig_rt, slice, 1, > + eth_ipv4_mcast_addr_base, mask_addr); > + mask_addr[5] = 0; > + netdev_for_each_mc_addr(ha, ndev) { > + /* skip addresses matching reserved slots */ > + if (!memcmp(eth_reserved_addr_base, ha->addr, 5) || > + !memcmp(eth_ipv4_mcast_addr_base, ha->addr, 5)) { > + netdev_dbg(ndev, "mcast skip %pM\n", ha->addr); > + continue; > + } > + > + if (slot >= FT1_NUM_SLOTS) { > + netdev_dbg(ndev, > + "can't add more than %d MC addresses, enabling allmulti\n", > + FT1_NUM_SLOTS); > + icssg_class_default(miig_rt, slice, 1, true); > + break; > + } > + > + netdev_dbg(ndev, "mcast add %pM\n", ha->addr); > + icssg_class_ft1_add_mcast(miig_rt, slice, slot, > + ha->addr, mask_addr); > + slot++; > + } > +} > + > /* required for SAV check */ > void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr) > { > diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/ethernet/ti/icssg/icssg_prueth.c > index e6eac01f9f99..7d9db9683e18 100644 > --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c > +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c > @@ -437,7 +437,7 @@ static int emac_ndo_open(struct net_device *ndev) > icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); > icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); > > - icssg_class_default(prueth->miig_rt, slice, 0); > + icssg_class_default(prueth->miig_rt, slice, 0, false); Should you be passing emac->is_sr1 instead of false? > > /* Notify the stack of the actual queue counts. */ > ret = netif_set_real_num_tx_queues(ndev, num_data_chn); > diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/ethernet/ti/icssg/icssg_prueth.h > index a8192e408941..faefd9351c39 100644 > --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h > +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h > @@ -283,7 +283,11 @@ extern const struct dev_pm_ops prueth_dev_pm_ops; > void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); > void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac); > void icssg_class_disable(struct regmap *miig_rt, int slice); > -void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); > +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti, > + bool is_sr1); > +void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice); > +void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice, > + struct net_device *ndev); > void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); > > /* config helpers */ -- cheers, -roger _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel