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Fri, 11 Oct 2024 17:58:00 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C685440048; Fri, 11 Oct 2024 17:56:29 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 35AE229ADFB; Fri, 11 Oct 2024 17:51:34 +0200 (CEST) Received: from [10.252.28.117] (10.252.28.117) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 11 Oct 2024 17:51:33 +0200 Message-ID: <3817a22e-72aa-45d3-8e16-19c703f7f7af@foss.st.com> Date: Fri, 11 Oct 2024 17:51:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] hwrng: stm32 - implement support for STM32MP25x platforms To: Marek Vasut , Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Lionel Debieve , , , , , , Yang Yingliang References: <20241007132721.168428-1-gatien.chevallier@foss.st.com> <20241007132721.168428-3-gatien.chevallier@foss.st.com> <2fad1566-49f9-4586-b0d4-8a4a12f9e69e@denx.de> <9283caeb-1b84-43c2-a8a4-6b43a6962f34@foss.st.com> <6a4cccb4-9e55-437d-925b-5f5bb1804159@foss.st.com> Content-Language: en-US From: Gatien CHEVALLIER In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.252.28.117] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241011_085818_286598_CCFCE286 X-CRM114-Status: GOOD ( 18.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/11/24 14:38, Marek Vasut wrote: > On 10/11/24 2:07 PM, Gatien CHEVALLIER wrote: >> >> >> On 10/11/24 13:24, Marek Vasut wrote: >>> On 10/11/24 11:55 AM, Gatien CHEVALLIER wrote: >>>> >>>> >>>> On 10/7/24 15:54, Marek Vasut wrote: >>>>> On 10/7/24 3:27 PM, Gatien Chevallier wrote: >>>>>> Implement the support for STM32MP25x platforms. On this platform, a >>>>>> security clock is shared between some hardware blocks. For the RNG, >>>>>> it is the RNG kernel clock. Therefore, the gate is no more shared >>>>>> between the RNG bus and kernel clocks as on STM32MP1x platforms and >>>>>> the bus clock has to be managed on its own. >>>>>> >>>>>> Signed-off-by: Gatien Chevallier >>>>> A bit of a higher-level design question -- can you use drivers/clk/ >>>>> clk-bulk.c clk_bulk_*() to handle all these disparate count of >>>>> clock easily ? >>>> >>>> Hi, I'd like to make sure that we enable the core clock before the bus >>>> clock so that the RNG hardware block can start its internal tests while >>>> we ungate the bus clock. It's not a strong opinion but it feels better. >>> Maybe this could still work if the struct clk_bulk_data {} is ordered >>> that way, so the bus clock are first, and the rest afterward ? >> >> I guess you meant, the core first. > > Err, yes, core. > >> Putting the bus clock first with the updated YAML doc generates a >> warning when checking the bindings. I guess what you propose is OK >> then. Core clock is defined first in the device tree. > > Not in DT, leave DT as-is. Look at struct clk_bulk_data , I think when > you use the clk_bulk_*() functions, you pass in a list of struct > clk_bulk_data, which each describes one clock, so just make sure that > list of struct clk_bulk_data in the driver is ordered the way you need > it to be ordered and you should be fine. I've sent a V2 with something that is functional but not aesthetic. You'll tell me if that's what you had in mind. Best regards, Gatien