* [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
@ 2019-05-02 23:47 Florian Fainelli
2019-05-06 7:25 ` John Garry
2019-05-13 11:19 ` Will Deacon
0 siblings, 2 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-05-02 23:47 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Peter Zijlstra, Catalin Marinas,
john.garry, Will Deacon, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
Changes in v2:
- added a shared directory for both Cortex-A57 and A72 (Will)
- removed unsupported ARMv8 v3 events (John)
.../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
2 files changed, 181 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
new file mode 100644
index 000000000000..0ac9b7927450
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
@@ -0,0 +1,179 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF",
+ },
+ {
+ "ArchStdEvent": "EXC_SVC",
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ",
+ },
+ {
+ "ArchStdEvent": "EXC_SMC",
+ },
+ {
+ "ArchStdEvent": "EXC_HVC",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ",
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 59cd8604b0bd..69a73957e35c 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,8 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
+0x00000000411fd07[[:xdigit:]],v1,arm/cortex-a57-a72,core
+0x00000000410fd08[[:xdigit:]],v1,arm/cortex-a57-a72,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-02 23:47 [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
@ 2019-05-06 7:25 ` John Garry
2019-05-10 19:49 ` Florian Fainelli
2019-05-13 11:19 ` Will Deacon
1 sibling, 1 reply; 6+ messages in thread
From: John Garry @ 2019-05-06 7:25 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 03/05/2019 00:47, Florian Fainelli wrote:
> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
> up to the RC_ST_SPEC (0x91) event with the exception of:
>
> - L1D_CACHE_REFILL_INNER (0x44)
> - L1D_CACHE_REFILL_OUTER (0x45)
> - L1D_TLB_RD (0x4E)
> - L1D_TLB_WR (0x4F)
> - L2D_TLB_REFILL_RD (0x5C)
> - L2D_TLB_REFILL_WR (0x5D)
> - L2D_TLB_RD (0x5E)
> - L2D_TLB_WR (0x5F)
> - STREX_SPEC (0x6F)
>
> Create an appropriate JSON file for mapping those events and update the
> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
> file.
I suppose you could have also created separate a72 and a57 folders, and
used a symbolic link for the json. That would have kept the folder
structure consistent and neat.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Apart from the above:
Reviewed-by: John Garry <john.garry@huawei.com>
> ---
> Changes in v2:
>
> - added a shared directory for both Cortex-A57 and A72 (Will)
> - removed unsupported ARMv8 v3 events (John)
>
> .../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
> 2 files changed, 181 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
>
> diff --git a/tools/perf/pmu-even
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-06 7:25 ` John Garry
@ 2019-05-10 19:49 ` Florian Fainelli
2019-05-13 11:14 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: Florian Fainelli @ 2019-05-10 19:49 UTC (permalink / raw)
To: John Garry, linux-kernel, Will Deacon, Mark Rutland
Cc: Peter Zijlstra, Catalin Marinas, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 5/6/19 12:25 AM, John Garry wrote:
> On 03/05/2019 00:47, Florian Fainelli wrote:
>> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
>> up to the RC_ST_SPEC (0x91) event with the exception of:
>>
>> - L1D_CACHE_REFILL_INNER (0x44)
>> - L1D_CACHE_REFILL_OUTER (0x45)
>> - L1D_TLB_RD (0x4E)
>> - L1D_TLB_WR (0x4F)
>> - L2D_TLB_REFILL_RD (0x5C)
>> - L2D_TLB_REFILL_WR (0x5D)
>> - L2D_TLB_RD (0x5E)
>> - L2D_TLB_WR (0x5F)
>> - STREX_SPEC (0x6F)
>>
>> Create an appropriate JSON file for mapping those events and update the
>> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
>> file.
>
> I suppose you could have also created separate a72 and a57 folders, and
> used a symbolic link for the json. That would have kept the folder
> structure consistent and neat.
Will, Mark, any preference on that? Either way works fine.
>
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> Apart from the above:
>
> Reviewed-by: John Garry <john.garry@huawei.com>
Thanks
>
>> ---
>> Changes in v2:
>>
>> - added a shared directory for both Cortex-A57 and A72 (Will)
>> - removed unsupported ARMv8 v3 events (John)
>>
>> .../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
>> 2 files changed, 181 insertions(+)
>> create mode 100644
>> tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
>>
>> diff --git a/tools/perf/pmu-even
>
--
Florian
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-10 19:49 ` Florian Fainelli
@ 2019-05-13 11:14 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2019-05-13 11:14 UTC (permalink / raw)
To: Florian Fainelli
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, John Garry,
linux-kernel, Arnaldo Carvalho de Melo, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On Fri, May 10, 2019 at 12:49:55PM -0700, Florian Fainelli wrote:
> On 5/6/19 12:25 AM, John Garry wrote:
> > On 03/05/2019 00:47, Florian Fainelli wrote:
> >> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
> >> up to the RC_ST_SPEC (0x91) event with the exception of:
> >>
> >> - L1D_CACHE_REFILL_INNER (0x44)
> >> - L1D_CACHE_REFILL_OUTER (0x45)
> >> - L1D_TLB_RD (0x4E)
> >> - L1D_TLB_WR (0x4F)
> >> - L2D_TLB_REFILL_RD (0x5C)
> >> - L2D_TLB_REFILL_WR (0x5D)
> >> - L2D_TLB_RD (0x5E)
> >> - L2D_TLB_WR (0x5F)
> >> - STREX_SPEC (0x6F)
> >>
> >> Create an appropriate JSON file for mapping those events and update the
> >> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
> >> file.
> >
> > I suppose you could have also created separate a72 and a57 folders, and
> > used a symbolic link for the json. That would have kept the folder
> > structure consistent and neat.
>
> Will, Mark, any preference on that? Either way works fine.
I'd personally avoid committing symbolic links if possible, so I'm fine
with your patch as-is.
Will
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-02 23:47 [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-06 7:25 ` John Garry
@ 2019-05-13 11:19 ` Will Deacon
2019-05-13 17:47 ` Florian Fainelli
1 sibling, 1 reply; 6+ messages in thread
From: Will Deacon @ 2019-05-13 11:19 UTC (permalink / raw)
To: Florian Fainelli
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, john.garry,
linux-kernel, Arnaldo Carvalho de Melo, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On Thu, May 02, 2019 at 04:47:04PM -0700, Florian Fainelli wrote:
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> index 59cd8604b0bd..69a73957e35c 100644
> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -13,6 +13,8 @@
> #
> #Family-model,Version,Filename,EventType
> 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
> +0x00000000411fd07[[:xdigit:]],v1,arm/cortex-a57-a72,core
The 4-bit variant field should be 0x0, not 0x1. In fact, I think we could do
the same for the revision field too and use 0x0 instead of [[:xdigit:]] for
Cortex-A53, no? Our implementation of get_cpuid_str() masks these out for us.
Am I missing something?
Will
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-13 11:19 ` Will Deacon
@ 2019-05-13 17:47 ` Florian Fainelli
0 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-05-13 17:47 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, john.garry,
linux-kernel, Arnaldo Carvalho de Melo, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 5/13/19 4:19 AM, Will Deacon wrote:
> On Thu, May 02, 2019 at 04:47:04PM -0700, Florian Fainelli wrote:
>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>> index 59cd8604b0bd..69a73957e35c 100644
>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>> @@ -13,6 +13,8 @@
>> #
>> #Family-model,Version,Filename,EventType
>> 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
>> +0x00000000411fd07[[:xdigit:]],v1,arm/cortex-a57-a72,core
>
> The 4-bit variant field should be 0x0, not 0x1. In fact, I think we could do
> the same for the revision field too and use 0x0 instead of [[:xdigit:]] for
> Cortex-A53, no? Our implementation of get_cpuid_str() masks these out for us.
>
> Am I missing something?
I blindly copied from the existing a53 entry without looking at how
get_cpuidr_str(), I will resubmit this and add a patch which removes the
[[:xdigit:]] for the A53 (and now Brahma-B53 entry) as well.
Thanks!
--
Florian
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2019-05-02 23:47 [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-06 7:25 ` John Garry
2019-05-10 19:49 ` Florian Fainelli
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2019-05-13 17:47 ` Florian Fainelli
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