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Tue, 29 Sep 2026 06:55:30 -0700 (PDT) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6acb9057b4csm872836a12.33.2026.09.29.06.55.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Sep 2026 06:55:29 -0700 (PDT) Message-ID: <3852b153-9be1-4ab4-803e-cb8a6de34879@linaro.org> Date: Tue, 29 Sep 2026 14:55:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64 To: Leo Yan Cc: Arnaldo Carvalho de Melo , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter , Mike Leach , Suzuki K Poulose , Suyash Mahar , Amir Ayupov References: <20260923-perf_cs_etm_fix_non_taken-v2-0-6ab8c07a5455@arm.com> <20260923-perf_cs_etm_fix_non_taken-v2-5-6ab8c07a5455@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20260923-perf_cs_etm_fix_non_taken-v2-5-6ab8c07a5455@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260929_065532_396073_2B1CB4DC X-CRM114-Status: GOOD ( 18.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 23/09/2026 16:21, Leo Yan wrote: > Use packet->last_instr_size in cs_etm__instr_size() instead of a > hard-coded value, allowing the decoder to supply the instruction size. > > Keep per-address decoding for T32. A range can mix 16-bit and 32-bit > instructions, so last_instr_size describes only the final instruction > and cannot determine the size at an arbitrary address in the range. > > Assisted-by: Codex:gpt-6 > Signed-off-by: Leo Yan > --- > tools/perf/util/cs-etm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index 2d1ab34f7b6b5a6331005c16c6a418d123c815eb..0163d93ac2d537a2190536e77d24628b4d707751 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -1358,8 +1358,7 @@ static inline int cs_etm__instr_size(struct cs_etm_queue *etmq, > if (packet->isa == CS_ETM_ISA_T32) > return cs_etm__t32_instr_size(etmq, tidq, packet, addr); > > - /* Otherwise, 4-byte instruction size for A32/A64 */ > - return 4; > + return packet->last_instr_size; Why not use last_instr_size for CS_ETM_ISA_T32 too? I'm wondering how and when this change actually makes a difference? last_instr_size isn't any better than '4' for any instruction in the range other than the last one, so it's not clear what the issue is. > } > > static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet) >