From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE6A4C43602 for ; Fri, 3 Jul 2026 06:26:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SSDpIKdc9KFNJYo6OB/lyw6kWfRv+7YvtWzJeQyNp50=; b=2Nze+bxp3A02RBR3+IM5lCgF+C UCaaCe8GkW1RLIOJpFJKKDQ77RluRIpbnMMUdk+yBvYfVf7CiHxkgnxHme3OjfruqoqohDyjIwBGZ zx7EFJpG7C5v09siSJ1otFhhU62qb5Hdj+V2JjMKLMrJ9glj4/fARtHeFN+0LjQcHG3C1Mc0jxuqQ IQLGUuIcNLyHcJ5TiQO8WvDRUFaR/7I9JzYV5lYGXoep73Y63Kh2dtPfwlbAtiqenE4gpx88BuNjz 8gAfuyX5zL64+aoAvSQY8+s31eEyxm9mdnsgrIakKS13nsTA7hYO3cgdai3AlDFuahLGDm6sQzFiI mym3t75Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wfXMT-000000069mt-1or1; Fri, 03 Jul 2026 06:26:53 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wfXMS-000000069mn-1zBL for linux-arm-kernel@lists.infradead.org; Fri, 03 Jul 2026 06:26:52 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 801CF6001A; Fri, 3 Jul 2026 06:26:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C0841F000E9; Fri, 3 Jul 2026 06:26:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783060011; bh=SSDpIKdc9KFNJYo6OB/lyw6kWfRv+7YvtWzJeQyNp50=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=VgN11bcR5iNSut0IP3G/sxsx1nT/rw0o3PK+DUrmLm84w8osacOg+hsgMFOCztnFj 3/MYWUDOCYjBlnG0MRUIEibl+rUc/RBpK5Gj+i16uFtCbJ/F8nRPa93v35J0txqNT3 jAJX+bqXlvpdwGdOsF1vZCqPv+r/ZsHqLDxj9nHvfPhpJRNbwC749rCwYQFw6eBe0g 57kDWjD8FJRZ84lCWwQrL791mPc2dXyIT5+LIJeHDZUuc7rp94ny3KFAxF+7XVMtQE 9IEASN3l43CkLH4AiLjFqZKiigaaqu9kIKznbwoM2miaxU+ilODq+QCMnsZ6P0pkKq cuiCNgmzxs9qA== Message-ID: <387ff0d7-256e-4b18-b864-37a0ec3c9d9d@kernel.org> Date: Fri, 3 Jul 2026 08:26:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 01/12] dt-bindings: soc: zte: Add zx297520v3 top clock and reset bindings To: =?UTF-8?Q?Stefan_D=C3=B6singer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260702-zx29clk-v6-0-377b704f80c4@gmail.com> <20260702-zx29clk-v6-1-377b704f80c4@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 02/07/2026 22:27, Stefan Dösinger wrote: > These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. The > separation of concerns between Top and Matrix and the interface between > them is poorly defined in the hardware, so the bindings list all > potential PLL clocks that might be passed between them. > > Generally every device has two clocks (one work clock, and one that > connects it to the bus, I call it PCLK), two reset bits (I don't know > what the difference is - sometimes asserting one is enough to reset the > device, sometimes both need to be asserted). PCLK and WCLK are > controlled by individual gates. Some devices have a mux and/or a > divider for their work clock. Some devices, like the GPIO controller, > only have reset bits and no clocks. > > The top clock controller is fed by a 26mhz external oscillator and has 4 > PLLs to generate other clock rates. ZTE's kernel mostly relies on the > boot ROM to set up PLLs, but one LTE-Related PLL is not configured > on some boards. Therefore my driver contains code to program PLLs. It > produces identical settings as the boot ROM for the pre-programmed > frequencies. > > Not all clocks will have an explicit user in the end. I am defining a > lot of them simply to shut them off. The boot loader sets up a few of > the proprietary timers, which will send regular IRQs (although the > kernel of course doesn't need to listen to them). I don't plan to add a > driver for the proprietary timer as I see no use for them - the ARM arch > timer works just fine. I will add a driver for the very similar > proprietary watchdog though. > > The clock list in this patch is pretty complete but not exhaustive. > There are other bits that are enabled, but I couldn't deduce what they > are controlling by trial and error. Some of them seem to do nothing. > Others cause an instant hang of the board when disabled. It is quite > likely that a handful more clocks will be added in the future, but not a > large number. > > Signed-off-by: Stefan Dösinger > > --- > > Changes v5->v6: > Set value for syscon-reboot example (Sashiko). It was my intention to > set only the lowest bit, and I think Sashiko is right that without > 'value' being set, all other bits are actively set to 0. It shouldn't > matter given my understanding of the hardware (afaics all other bits are > ignored), but actively clearing bits was not my intention. > > I haven't changed the name match for "syscon-reboot". I see plenty of > examples of hardcoding this string as opposed to having a regex for > syscon-reboot@12345678 in other bindings. > > Changes v4->v5: > > Rename from zte,zx297520v3-topclk to zte,zx297520v3-topcrm and move to > soc/zte > Fix path in MAINTAINERS > Add syscon-reboot node to the binding > Give the USB and HSIC PHY resets their own reset control > --- > .../bindings/soc/zte/zte,zx297520v3-topcrm.yaml | 86 +++++++++++++++++++ > MAINTAINERS | 3 + > include/dt-bindings/clock/zte,zx297520v3-clk.h | 97 ++++++++++++++++++++++ > include/dt-bindings/reset/zte,zx297520v3-reset.h | 32 +++++++ > 4 files changed, 218 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml > new file mode 100644 > index 000000000000..5a5d97120056 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml > @@ -0,0 +1,86 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/zte/zte,zx297520v3-topcrm.yaml# Also, this cannot be placed in soc. Clock and reset controllers DO NOT go to the soc directory. Place in it clocks. A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23 Best regards, Krzysztof