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From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com,
	linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org,
	linux-kernel@vger.kernel.org, swboyd@chromium.org,
	peterz@infradead.org, denik@google.com, leo.yan@linaro.org,
	linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH 2/2] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register
Date: Mon, 28 Sep 2020 16:52:55 +0530	[thread overview]
Message-ID: <388adccec089823fcd6d009892ad95a1@codeaurora.org> (raw)
In-Reply-To: <0e0bc2fd-0449-35bc-882a-3b942a55fda4@arm.com>

Hi Suzuki,

On 2020-09-28 16:35, Suzuki K Poulose wrote:
> Hi Sai,
> 
> On 09/27/2020 05:20 PM, Sai Prakash Ranjan wrote:
>> In commit f188b5e76aae ("coresight: etm4x: Save/restore state
>> across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
>> value was saved in trcvmidcctlr0 state variable which is used to
>> store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
>> same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
>> in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
>> variable available for TRCVMIDCCTLR1, so use it.
>> 
>> Fixes: 8b44fdfef6a2 ("coresight: etm4x: Allow etm4x to be built as a 
>> module")
> 
> Why is this commit in question ?

My bad sorry, I thought there are two commits which touch this hunk of 
code,
but I see now that the module code just renamed the file, so this fixes 
tag
is not required.

> 
>> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU 
>> low power states")
> 
> I believe this is the right fixes tag.
> 

Yes, I will resend with only this fixes tag.

>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c 
>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index de76d57850bc..abd706b216ac 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -1243,7 +1243,7 @@ static int etm4_cpu_save(struct etmv4_drvdata 
>> *drvdata)
>>   	state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
>>     	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
>> -	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
>> +	state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1);
>>     	state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
>>   @@ -1353,7 +1353,7 @@ static void etm4_cpu_restore(struct 
>> etmv4_drvdata *drvdata)
>>   	writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
>>     	writel_relaxed(state->trcvmidcctlr0, drvdata->base + 
>> TRCVMIDCCTLR0);
>> -	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
>> +	writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1);
>> 
> 
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Thanks,
Sai

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      reply	other threads:[~2020-09-28 11:24 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-27 16:20 [PATCH 0/2] Coresight ETF NULL pointer dereference and ETM save/restore fixes Sai Prakash Ranjan
2020-09-27 16:20 ` [RFC PATCH 1/2] coresight: tmc-etf: Fix NULL pointer dereference in tmc_enable_etf_sink_perf() Sai Prakash Ranjan
2020-09-27 16:20 ` [PATCH 2/2] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register Sai Prakash Ranjan
2020-09-28 11:05   ` Suzuki K Poulose
2020-09-28 11:22     ` Sai Prakash Ranjan [this message]

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