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Januar 2025, 04:36:33 CET schrieb Peng Fan: > > Subject: Re: [PATCH v6 2/2] nvmem: imx-ocotp-ele: Support accessing > > controller for i.MX9 > >=20 > > Hi, > >=20 > > Am Dienstag, 21. Januar 2025, 16:05:32 CET schrieb Peng Fan (OSS): > > > From: Peng Fan > > > > > > i.MX9 OCOTP supports a specific peripheral or function being fused > > > which means disabled, so > > > - Introduce ocotp_access_gates to be container of efuse gate info > > > - Iterate all nodes to check accessing permission. If not > > > allowed to be accessed, detach the node > > > > > > Signed-off-by: Peng Fan > > > --- > > > drivers/nvmem/Kconfig | 3 + > > > drivers/nvmem/imx-ocotp-ele.c | 172 > > > +++++++++++++++++++++++++++++++++++++++++- > > > 2 files changed, 174 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index > > > > > 8671b7c974b933e147154bb40b5d41b5730518d2..77cc496fd5e0e1af > > d753534b56fe > > > 1f5ef3e3ec55 100644 > > > --- a/drivers/nvmem/Kconfig > > > +++ b/drivers/nvmem/Kconfig > > > @@ -93,6 +93,9 @@ config NVMEM_IMX_OCOTP_ELE > > > This is a driver for the On-Chip OTP Controller (OCOTP) > > > available on i.MX SoCs which has ELE. > > > > > > + If built as modules, any other driver relying on this working > > > + as access controller also needs to be a module as well. > > > + > > > config NVMEM_IMX_OCOTP_SCU > > > tristate "i.MX8 SCU On-Chip OTP Controller support" > > > depends on IMX_SCU > > > diff --git a/drivers/nvmem/imx-ocotp-ele.c > > > b/drivers/nvmem/imx-ocotp-ele.c index > > > > > ca6dd71d8a2e29888c6e556aaea116c1a967cb5f..5ea6d959ce38760ee > > ed44a989992 > > > fb35c462c0b4 100644 > > > --- a/drivers/nvmem/imx-ocotp-ele.c > > > +++ b/drivers/nvmem/imx-ocotp-ele.c > > > @@ -5,6 +5,8 @@ > > > * Copyright 2023 NXP > > > */ > > > > > > +#include > > > +#include > > > #include > > > #include > > > #include > > > @@ -27,6 +29,7 @@ struct ocotp_map_entry { }; > > > > > > struct ocotp_devtype_data { > > > + const struct ocotp_access_gates *access_gates; > > > u32 reg_off; > > > char *name; > > > u32 size; > > > @@ -36,6 +39,20 @@ struct ocotp_devtype_data { > > > struct ocotp_map_entry entry[]; > > > }; > > > > > > +#define OCOTP_MAX_NUM_GATE_WORDS 4 > > > + > > > +struct access_gate { > > > + u32 word; > > > + u32 mask; > > > +}; > > > + > > > +struct ocotp_access_gates { > > > + u32 num_words; > > > + u32 words[OCOTP_MAX_NUM_GATE_WORDS]; > > > + u32 num_gates; > > > + struct access_gate *gates; > > > +}; > > > + > > > struct imx_ocotp_priv { > > > struct device *dev; > > > void __iomem *base; > > > @@ -131,6 +148,82 @@ static void > > imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem, > > > cell->read_post_process =3D imx_ocotp_cell_pp; } > > > > > > +static int imx_ele_ocotp_check_access(struct imx_ocotp_priv *priv, > > > +u32 id) { > > > + const struct ocotp_access_gates *access_gates =3D priv->data- > > >access_gates; > > > + void __iomem *reg =3D priv->base + priv->data->reg_off; > > > + u32 word, mask, val; > > > + > > > + if (id >=3D access_gates->num_gates) { > > > + dev_err(priv->config.dev, "Index %d too large\n", id); > > > + return -EACCES; > > > + } > > > + > > > + word =3D access_gates->gates[id].word; > > > + mask =3D access_gates->gates[id].mask; > > > + > > > + reg =3D priv->base + priv->data->reg_off + (word << 2); > > > + val =3D readl(reg); > > > + > > > + dev_dbg(priv->config.dev, "id:%d word:%d mask:0x%08x\n", > > id, word, mask); > > > + /* true means not allow access */ > > > + if (val & mask) > > > + return -EACCES; > > > + > > > + return 0; > > > +} > > > + > > > +static int imx_ele_ocotp_grant_access(struct imx_ocotp_priv *priv, > > > +struct device_node *parent) { > > > + struct device *dev =3D priv->config.dev; > > > + > > > + for_each_available_child_of_node_scoped(parent, child) { > > > + struct of_phandle_args args; > > > + u32 id, idx =3D 0; > > > + > > > + while (!of_parse_phandle_with_args(child, "access- > > controllers", > > > + "#access- > > controller-cells", > > > + idx++, &args)) { > > > + of_node_put(args.np); > > > + if (args.np !=3D dev->of_node) > > > + continue; > > > + > > > + /* Only support one cell */ > > > + if (args.args_count !=3D 1) { > > > + dev_err(dev, "wrong args count\n"); > > > + continue; > > > + } > > > + > > > + id =3D args.args[0]; > > > + > > > + dev_dbg(dev, "Checking node: %pOF > > gate: %d\n", child, id); > > > + > > > + if (imx_ele_ocotp_check_access(priv, id)) { > > > + of_detach_node(child); > > > + dev_info(dev, "%pOF: Not granted, > > device driver will not be probed\n", > > > + child); > > > + } > > > + } > > > + > > > + imx_ele_ocotp_grant_access(priv, child); > > > + } > > > + > > > + return 0; > > > +} > > > + > > > +static int imx_ele_ocotp_access_control(struct imx_ocotp_priv *priv) > > > +{ > > > + struct device_node *root __free(device_node) =3D > > > +of_find_node_by_path("/"); > > > + > > > + if (!priv->data->access_gates) > > > + return 0; > > > + > > > + /* This should never happen */ > > > + WARN_ON(!root); > >=20 > > Even if you warning something is wrong, aka root =3D=3D NULL, you are s= till > > using it on imx_ele_ocotp_grant_access(). Just return early. > >=20 > > if (WARN_ON(!)) > > return -EINVAL; >=20 > Hmm, If this really happens, return early or not does not make much sense. > Does it really matter here? Why does it not make much sense? You already know something is wrong, aka you have a NULL pointer, so it makes even less sense to continue. I've skipped through the sources and looked for 'WARN_ON(!)', most of the times it is actually checked for early returns. Best regards, Alexander =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/