[PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T

[PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T

["Martin Holovský (Probably Nothing s.r.o.)"]

The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
Currently only one interface is functional because the PCIe controller
nodes lack the necessary reset GPIO configuration.

Without the reset-gpios property, the RTL8125B PHYs remain in reset state
and are not enumerated by the PCIe bus. This results in only one Ethernet
interface being detected, or none at all depending on U-Boot initialization.

This patch adds the missing configuration for both PCIe controllers:
- Enables both pcie2x1l0 and pcie2x1l2 nodes (status = "okay")
- Configures reset GPIOs (GPIO4_PA5 and GPIO3_PB0 respectively)
- Adds corresponding pinctrl definitions

With this change, both 2.5GbE interfaces are properly detected and
functional on the Rock 5T.

Tested on Radxa Rock 5T v1.2 running Linux 6.12.


---
 .../boot/dts/rockchip/rk3588-rock-5t.dts      | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
index 0dd90c744380..aeb8e0d42f09 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -68,6 +68,20 @@ &pcie2x1l1 {
 	status = "okay";
 };
 
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_2_rst>;
+	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
 &pcie30phy {
 	data-lanes = <1 1 2 2>;
 };
@@ -101,6 +115,15 @@ pcie2 {
 		pcie2_1_rst: pcie2-1-rst {
 			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_2_rst: pcie2-2-rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
 		pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
 			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
-- 
2.52.0

Re: [PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T

[Heiko Stuebner]

On Fri, 12 Dec 2025 17:23:35 +0100, "Martin Holovský (Probably Nothing s.r.o. )" wrote:
> The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
> connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
> Currently only one interface is functional because the PCIe controller
> nodes lack the necessary reset GPIO configuration.
> 
> Without the reset-gpios property, the RTL8125B PHYs remain in reset state
> and are not enumerated by the PCIe bus. This results in only one Ethernet
> interface being detected, or none at all depending on U-Boot initialization.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T
      commit: 96029ffeccf677b1e4baa98f30909a83a485b6d7

I've resorted both the pcie phandles as well as the pinctrl entries
pcie2-0 comes before pcie2-1 etc :-) .

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: [PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T

[Heiko Stübner]

Am Montag, 15. Dezember 2025, 14:51:03 Mitteleuropäische Normalzeit schrieb Heiko Stuebner:
> 
> On Fri, 12 Dec 2025 17:23:35 +0100, "Martin Holovský (Probably Nothing s.r.o. )" wrote:
> > The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
> > connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
> > Currently only one interface is functional because the PCIe controller
> > nodes lack the necessary reset GPIO configuration.
> > 
> > Without the reset-gpios property, the RTL8125B PHYs remain in reset state
> > and are not enumerated by the PCIe bus. This results in only one Ethernet
> > interface being detected, or none at all depending on U-Boot initialization.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [1/1] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T
>       commit: 96029ffeccf677b1e4baa98f30909a83a485b6d7
> 
> I've resorted both the pcie phandles as well as the pinctrl entries
> pcie2-0 comes before pcie2-1 etc :-) .

and dropped again.

Please resend this patch with a proper Signed-off-by line, as stated
by the developers certificate of origin.

Also, what is this probably nothing s.r.o?

Heiko

Re: [PATCH] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T

["Martin Holovský (Probably Nothing s.r.o.)"]

Perfect, thanks a lot!

> On 15. 12. 2025, at 14:51, Heiko Stuebner <heiko@sntech.de> wrote:
> 
> 
> On Fri, 12 Dec 2025 17:23:35 +0100, "Martin Holovský (Probably Nothing s.r.o. )" wrote:
>> The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
>> connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
>> Currently only one interface is functional because the PCIe controller
>> nodes lack the necessary reset GPIO configuration.
>> 
>> Without the reset-gpios property, the RTL8125B PHYs remain in reset state
>> and are not enumerated by the PCIe bus. This results in only one Ethernet
>> interface being detected, or none at all depending on U-Boot initialization.
>> 
>> [...]
> 
> Applied, thanks!
> 
> [1/1] arm64: dts: rockchip: enable dual 2.5GbE on Rock 5T
>      commit: 96029ffeccf677b1e4baa98f30909a83a485b6d7
> 
> I've resorted both the pcie phandles as well as the pinctrl entries
> pcie2-0 comes before pcie2-1 etc :-) .
> 
> Best regards,
> -- 
> Heiko Stuebner <heiko@sntech.de>

[PATCH v2] arm64: dts: rockchip: enable both 2.5GbE ports on Rock 5T

["Martin Holovský (Probably Nothing s.r.o.)"]

The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
Currently only one interface is functional because the PCIe controller
nodes lack the necessary reset GPIO configuration.

Without the reset-gpios property, the RTL8125B PHYs remain in reset state
and are not enumerated by the PCIe bus. This results in only one Ethernet
interface being detected, or none at all depending on U-Boot initialization.

This patch adds the missing configuration for both PCIe controllers:
- Enables both pcie2x1l0 and pcie2x1l2 nodes (status = "okay")
- Configures reset GPIOs (GPIO4_PA5 and GPIO3_PB0 respectively)
- Adds corresponding pinctrl definitions

With this change, both 2.5GbE interfaces are properly detected and
functional on the Rock 5T.

Tested on Radxa Rock 5T v1.2 running Linux 6.12.

Signed-off-by: Martin Holovsky <mh@probably.group>
---
Changes in v2:
- Sorted pcie nodes alphanumerically
- Sorted pinctrl nodes alphanumerically
- Added Signed-off-by line

 .../boot/dts/rockchip/rk3588-rock-5t.dts      | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
index 0dd90c744380..aeb8e0d42f09 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -68,10 +68,24 @@ &pcie2x1l1 {
 	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_2_rst>;
+	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
 &pcie30phy {
 	data-lanes = <1 1 2 2>;
 };
@@ -101,6 +115,14 @@ pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
 		pcie2_1_rst: pcie2-1-rst {
 			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie2_2_rst: pcie2-2-rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
 		pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
 			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
-- 
2.52.0

Re: [PATCH v2] arm64: dts: rockchip: enable both 2.5GbE ports on Rock 5T

[FUKAUMI Naoki]

Hi Martin,

Please check
  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi?h=v6.18#n469

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 12/18/25 15:27, "Martin Holovský (Probably Nothing s.r.o.)" wrote:
> The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
> connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
> Currently only one interface is functional because the PCIe controller
> nodes lack the necessary reset GPIO configuration.
> 
> Without the reset-gpios property, the RTL8125B PHYs remain in reset state
> and are not enumerated by the PCIe bus. This results in only one Ethernet
> interface being detected, or none at all depending on U-Boot initialization.
> 
> This patch adds the missing configuration for both PCIe controllers:
> - Enables both pcie2x1l0 and pcie2x1l2 nodes (status = "okay")
> - Configures reset GPIOs (GPIO4_PA5 and GPIO3_PB0 respectively)
> - Adds corresponding pinctrl definitions
> 
> With this change, both 2.5GbE interfaces are properly detected and
> functional on the Rock 5T.
> 
> Tested on Radxa Rock 5T v1.2 running Linux 6.12.
> 
> Signed-off-by: Martin Holovsky <mh@probably.group>
> ---
> Changes in v2:
> - Sorted pcie nodes alphanumerically
> - Sorted pinctrl nodes alphanumerically
> - Added Signed-off-by line
> 
>   .../boot/dts/rockchip/rk3588-rock-5t.dts      | 28 +++++++++++++++++++
>   1 file changed, 28 insertions(+)
> 
>   		};
> +
> +		pcie2_2_rst: pcie2-2-rst {
> +			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
>   		pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
>   			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
>   		};
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> index 0dd90c744380..aeb8e0d42f09 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> @@ -68,10 +68,24 @@ &pcie2x1l1 {
>   	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
>   	status = "okay";
>   };
>   
> +&pcie2x1l0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_0_rst>;
> +	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&pcie2x1l2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_2_rst>;
> +	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
>   &pcie30phy {
>   	data-lanes = <1 1 2 2>;
>   };
> @@ -101,6 +115,14 @@ pcie2 {
> +		pcie2_0_rst: pcie2-0-rst {
> +			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
>   		pcie2_1_rst: pcie2-1-rst {
>   			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;

Re: [PATCH v2] arm64: dts: rockchip: enable both 2.5GbE ports on Rock 5T

[Nicolas Frattaroli]

On Thursday, 18 December 2025 07:27:06 Central European Standard Time Martin Holovský (Probably Nothing s.r.o.) wrote:
> The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
> connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
> Currently only one interface is functional because the PCIe controller
> nodes lack the necessary reset GPIO configuration.
> 
> Without the reset-gpios property, the RTL8125B PHYs remain in reset state
> and are not enumerated by the PCIe bus. This results in only one Ethernet
> interface being detected, or none at all depending on U-Boot initialization.
> 
> This patch adds the missing configuration for both PCIe controllers:
> - Enables both pcie2x1l0 and pcie2x1l2 nodes (status = "okay")
> - Configures reset GPIOs (GPIO4_PA5 and GPIO3_PB0 respectively)
> - Adds corresponding pinctrl definitions
> 
> With this change, both 2.5GbE interfaces are properly detected and
> functional on the Rock 5T.
> 
> Tested on Radxa Rock 5T v1.2 running Linux 6.12.
> 
> Signed-off-by: Martin Holovsky <mh@probably.group>
> ---
> Changes in v2:
> - Sorted pcie nodes alphanumerically
> - Sorted pinctrl nodes alphanumerically
> - Added Signed-off-by line
> 
>  .../boot/dts/rockchip/rk3588-rock-5t.dts      | 28 +++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> index 0dd90c744380..aeb8e0d42f09 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> @@ -68,10 +68,24 @@ &pcie2x1l1 {
>  	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
>  	status = "okay";
>  };
>  
> +&pcie2x1l0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_0_rst>;
> +	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&pcie2x1l2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie2_2_rst>;
> +	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
>  &pcie30phy {
>  	data-lanes = <1 1 2 2>;
>  };
> @@ -101,6 +115,14 @@ pcie2 {
> +		pcie2_0_rst: pcie2-0-rst {
> +			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
>  		pcie2_1_rst: pcie2-1-rst {
>  			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
> +
> +		pcie2_2_rst: pcie2-2-rst {
> +			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
>  		pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
>  			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
> 

This stuff is already in rk3588-rock-5b-5bp-5t.dtsi. Ergo, this patch
does nothing at all. What are you actually trying to solve?

Heiko, please don't apply this.

Kind regards,
Nicolas Frattaroli

Re: [PATCH v2] arm64: dts: rockchip: enable both 2.5GbE ports on Rock 5T

[Heiko Stuebner]

Am Freitag, 19. Dezember 2025, 14:06:12 Mitteleuropäische Normalzeit schrieb Nicolas Frattaroli:
> On Thursday, 18 December 2025 07:27:06 Central European Standard Time Martin Holovský (Probably Nothing s.r.o.) wrote:
> > The Radxa Rock 5T board features two RTL8125B 2.5GbE Ethernet controllers
> > connected via PCIe lanes pcie2x1l0 (fe170000) and pcie2x1l2 (fe190000).
> > Currently only one interface is functional because the PCIe controller
> > nodes lack the necessary reset GPIO configuration.
> > 
> > Without the reset-gpios property, the RTL8125B PHYs remain in reset state
> > and are not enumerated by the PCIe bus. This results in only one Ethernet
> > interface being detected, or none at all depending on U-Boot initialization.
> > 
> > This patch adds the missing configuration for both PCIe controllers:
> > - Enables both pcie2x1l0 and pcie2x1l2 nodes (status = "okay")
> > - Configures reset GPIOs (GPIO4_PA5 and GPIO3_PB0 respectively)
> > - Adds corresponding pinctrl definitions
> > 
> > With this change, both 2.5GbE interfaces are properly detected and
> > functional on the Rock 5T.
> > 
> > Tested on Radxa Rock 5T v1.2 running Linux 6.12.
> > 
> > Signed-off-by: Martin Holovsky <mh@probably.group>
> > ---
> > Changes in v2:
> > - Sorted pcie nodes alphanumerically
> > - Sorted pinctrl nodes alphanumerically
> > - Added Signed-off-by line
> > 
> >  .../boot/dts/rockchip/rk3588-rock-5t.dts      | 28 +++++++++++++++++++
> >  1 file changed, 28 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> > index 0dd90c744380..aeb8e0d42f09 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> > @@ -68,10 +68,24 @@ &pcie2x1l1 {
> >  	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
> >  	status = "okay";
> >  };
> >  
> > +&pcie2x1l0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie2_0_rst>;
> > +	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
> > +	status = "okay";
> > +};
> > +
> > +&pcie2x1l2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie2_2_rst>;
> > +	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
> > +	status = "okay";
> > +};
> > +
> >  &pcie30phy {
> >  	data-lanes = <1 1 2 2>;
> >  };
> > @@ -101,6 +115,14 @@ pcie2 {
> > +		pcie2_0_rst: pcie2-0-rst {
> > +			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> > +		};
> > +
> >  		pcie2_1_rst: pcie2-1-rst {
> >  			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
> >  		};
> > +
> > +		pcie2_2_rst: pcie2-2-rst {
> > +			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> > +		};
> > +
> >  		pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
> >  			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
> >  		};
> > 
> 
> This stuff is already in rk3588-rock-5b-5bp-5t.dtsi. Ergo, this patch
> does nothing at all. What are you actually trying to solve?
> 
> Heiko, please don't apply this.

Thanks for the heads-up, both to you and Naoki :-)

Heiko