From: Marc Zyngier <maz@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: Barry Song <song.bao.hua@hisilicon.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Steve Capper <steve.capper@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Mike Rapoport <rppt@linux.ibm.com>, Wei Li <liwei213@huawei.com>,
butao@hisilicon.com, Will Deacon <will@kernel.org>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
fengbaopeng2@hisilicon.com
Subject: Re: [PATCH] arm64: mm: decrease the section size to reduce the memory reserved for the page map
Date: Mon, 07 Dec 2020 09:35:06 +0000 [thread overview]
Message-ID: <390f5f441d99a832f4b2425b46f6d971@kernel.org> (raw)
In-Reply-To: <CAMj1kXGQ-CeYcbS-hc+Yy8DKHm2t-RYsLu4+7wOG1bWuJqkjGQ@mail.gmail.com>
On 2020-12-07 09:09, Ard Biesheuvel wrote:
> (+ Marc)
>
> On Fri, 4 Dec 2020 at 12:14, Will Deacon <will@kernel.org> wrote:
>>
>> On Fri, Dec 04, 2020 at 09:44:43AM +0800, Wei Li wrote:
>> > For the memory hole, sparse memory model that define SPARSEMEM_VMEMMAP
>> > do not free the reserved memory for the page map, decrease the section
>> > size can reduce the waste of reserved memory.
>> >
>> > Signed-off-by: Wei Li <liwei213@huawei.com>
>> > Signed-off-by: Baopeng Feng <fengbaopeng2@hisilicon.com>
>> > Signed-off-by: Xia Qing <saberlily.xia@hisilicon.com>
>> > ---
>> > arch/arm64/include/asm/sparsemem.h | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h
>> > index 1f43fcc79738..8963bd3def28 100644
>> > --- a/arch/arm64/include/asm/sparsemem.h
>> > +++ b/arch/arm64/include/asm/sparsemem.h
>> > @@ -7,7 +7,7 @@
>> >
>> > #ifdef CONFIG_SPARSEMEM
>> > #define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS
>> > -#define SECTION_SIZE_BITS 30
>> > +#define SECTION_SIZE_BITS 27
>>
>> We chose '30' to avoid running out of bits in the page flags. What
>> changed?
>>
>> With this patch, I can trigger:
>>
>> ./include/linux/mmzone.h:1170:2: error: Allocator MAX_ORDER exceeds
>> SECTION_SIZE
>> #error Allocator MAX_ORDER exceeds SECTION_SIZE
>>
>> if I bump up NR_CPUS and NODES_SHIFT.
>>
>
> Does this mean we will run into problems with the GICv3 ITS LPI tables
> again if we are forced to reduce MAX_ORDER to fit inside
> SECTION_SIZE_BITS?
Most probably. We are already massively constraint on platforms
such as TX1, and dividing the max allocatable range by 8 isn't
going to make it work any better...
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2020-12-07 9:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 1:44 [PATCH] arm64: mm: decrease the section size to reduce the memory reserved for the page map Wei Li
2020-12-04 1:50 ` Song Bao Hua (Barry Song)
2020-12-04 11:13 ` Will Deacon
2020-12-04 11:44 ` Mike Rapoport
2020-12-07 1:40 ` Song Bao Hua (Barry Song)
2020-12-07 7:30 ` Anshuman Khandual
2020-12-07 7:47 ` Song Bao Hua (Barry Song)
2020-12-07 9:09 ` Ard Biesheuvel
2020-12-07 9:35 ` Marc Zyngier [this message]
2020-12-07 9:42 ` Mike Rapoport
2020-12-07 9:49 ` Ard Biesheuvel
2020-12-07 10:04 ` Mike Rapoport
2020-12-07 10:39 ` Anshuman Khandual
2020-12-07 12:07 ` Wei Li
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