From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A38CC10F1A for ; Tue, 7 May 2024 10:52:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vnWL+1ehgnFdbPtYd9hp2zadTS4aayXZXbcfbEh7kt4=; b=HQmAvvb/R+rSdo O6QFv01ENXjgNj4Eq7YL24rAJV/k+o+fmFguHIRujLcsfMZGhvyjjOXIKWvYWVZ/pGEBn8rnwNHpp HKTUA0EWU/uTq8WfudOYkMpeGMylWs+bt8AYtoYZ+Re2CVob0gr0pj93PRMa9OwgKyF+l5yowcIek qxhFOn5TXSj/QhifXuxUg/rVZuF7C10U9nNVBN32zVMi98GDru7g0Ur3KJKBWDvK+qXHG/ReP0hzb jXx8zaQ/GRblE2FUUNnYgcP+LVc3o2Mx7jev4JqAmLxfOGmTZKKuolrHsyl7OymWK/JS1e68OxYzq nbL1Qwq6CxV669lRkxsg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4IR9-0000000Abws-1B4s; Tue, 07 May 2024 10:52:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4IR6-0000000Abw6-1Dpf for linux-arm-kernel@lists.infradead.org; Tue, 07 May 2024 10:52:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62F461063; Tue, 7 May 2024 03:53:04 -0700 (PDT) Received: from [10.1.197.1] (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BD45C3F587; Tue, 7 May 2024 03:52:35 -0700 (PDT) Message-ID: <3923dc07-c037-452a-9e77-d407703876cd@arm.com> Date: Tue, 7 May 2024 11:52:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/17] coresight: Use per-sink trace ID maps for Perf sessions To: James Clark , linux-perf-users@vger.kernel.org, gankulkarni@os.amperecomputing.com, scclevenger@os.amperecomputing.com, coresight@lists.linaro.org, mike.leach@linaro.org Cc: Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , John Garry , Will Deacon , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com References: <20240429152207.479221-1-james.clark@arm.com> <20240429152207.479221-16-james.clark@arm.com> Content-Language: en-US From: Suzuki K Poulose In-Reply-To: <20240429152207.479221-16-james.clark@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240507_035240_566080_9235D817 X-CRM114-Status: GOOD ( 28.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 29/04/2024 16:22, James Clark wrote: > This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs > as long as there are fewer than that many ETMs connected to each sink. > > Each sink owns its own trace ID map, and any Perf session connecting to > that sink will allocate from it, even if the sink is currently in use by > other users. This is similar to the existing behavior where the dynamic > trace IDs are constant as long as there is any concurrent Perf session > active. It's not completely optimal because slightly more IDs will be > used than necessary, but the optimal solution involves tracking the PIDs > of each session and allocating ID maps based on the session owner. This > is difficult to do with the combination of per-thread and per-cpu modes > and some scheduling issues. The complexity of this isn't likely to worth > it because even with multiple users they'd just see a difference in the > ordering of ID allocations rather than hitting any limits (unless the > hardware does have too many ETMs connected to one sink). > > Signed-off-by: James Clark > --- > drivers/hwtracing/coresight/coresight-core.c | 10 ++++++++++ > drivers/hwtracing/coresight/coresight-etm-perf.c | 15 ++++++++------- > include/linux/coresight.h | 1 + > 3 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 9fc6f6b863e0..d1adff467670 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -902,6 +902,7 @@ static void coresight_device_release(struct device *dev) > struct coresight_device *csdev = to_coresight_device(dev); > > fwnode_handle_put(csdev->dev.fwnode); > + free_percpu(csdev->perf_id_map.cpu_map); > kfree(csdev); > } > > @@ -1159,6 +1160,14 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > csdev->dev.fwnode = fwnode_handle_get(dev_fwnode(desc->dev)); > dev_set_name(&csdev->dev, "%s", desc->name); > > + if (csdev->type == CORESIGHT_DEV_TYPE_SINK || > + csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) { > + csdev->perf_id_map.cpu_map = alloc_percpu(atomic_t); > + if (!csdev->perf_id_map.cpu_map) { > + ret = -ENOMEM; > + goto err_out; > + } > + } > /* > * Make sure the device registration and the connection fixup > * are synchronised, so that we don't see uninitialised devices > @@ -1216,6 +1225,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > err_out: > /* Cleanup the connection information */ > coresight_release_platform_data(NULL, desc->dev, desc->pdata); > + kfree(csdev); > return ERR_PTR(ret); > } > EXPORT_SYMBOL_GPL(coresight_register); > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index 177cecae38d9..86ca1a9d09a7 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -229,10 +229,13 @@ static void free_event_data(struct work_struct *work) > struct list_head **ppath; > > ppath = etm_event_cpu_path_ptr(event_data, cpu); > - if (!(IS_ERR_OR_NULL(*ppath))) > + if (!(IS_ERR_OR_NULL(*ppath))) { > + struct coresight_device *sink = coresight_get_sink(*ppath); > + > + coresight_trace_id_put_cpu_id(cpu, &sink->perf_id_map); > coresight_release_path(*ppath); > + } > *ppath = NULL; > - coresight_trace_id_put_cpu_id(cpu, coresight_trace_id_map_default()); > } > > /* mark perf event as done for trace id allocator */ > @@ -401,8 +404,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > } > > /* ensure we can allocate a trace ID for this CPU */ > - trace_id = coresight_trace_id_get_cpu_id(cpu, > - coresight_trace_id_map_default()); > + trace_id = coresight_trace_id_get_cpu_id(cpu, &sink->perf_id_map); We could either store the perf_id_map or the traceid itself in the event_data isn't it ? Rather than passing the idmap to enable_source ? Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel