From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F1E8C4360F for ; Tue, 2 Apr 2019 15:43:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51C7E20657 for ; Tue, 2 Apr 2019 15:43:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AEf0GSTK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 51C7E20657 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eCgGR6So4moBtuU1604PpRC+/7E/yX1SxlsrSMTPI8o=; b=AEf0GSTKXoKun6 FzHftiHZzhdtwzVyfKF00+VUFrG6KRRF10O6aP8J8r7uZg31ifQO2xg3ud400WHZKDc/mshy2Uz9t yUAbXokAXnEAJaYeSHDQ5XM8C8uJ009KQiWH6n/JfFkTvk42C0PedbWgrOE+ud6Yjp4MnVzDZWm8y XCYMC2Ptq7UZZ1hKsNcnI3vfMlNLQ9NQmzUQrbo9psfUe+6YkrFMe+4qflRWcJwiV63jyqbJ0Vxhf PthO9NFHeF2jj1epGheVWEvDwGsGlmJSSgwiLUtSs3KryBtNZU9AdH8ayK4ay/erfL4pQXTAA9tVJ +E8U/rL/KN/8aL2LJRYw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBLZ4-0001Re-L8; Tue, 02 Apr 2019 15:43:06 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBLZ0-0001R9-O8 for linux-arm-kernel@lists.infradead.org; Tue, 02 Apr 2019 15:43:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59719374; Tue, 2 Apr 2019 08:43:02 -0700 (PDT) Received: from [10.1.197.45] (e112298-lin.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 427E53F721; Tue, 2 Apr 2019 08:43:00 -0700 (PDT) Subject: Re: [PATCH] arm64: perf: Do not write event type for cycle counter To: Mark Rutland References: <1553766545-27692-1-git-send-email-julien.thierry@arm.com> <20190401080217.r27dgjc43xa5ruzr@blommer> From: Julien Thierry Message-ID: <399b05e9-e309-d5c5-4d41-a672eb4c5d5c@arm.com> Date: Tue, 2 Apr 2019 16:42:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190401080217.r27dgjc43xa5ruzr@blommer> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190402_084302_792497_778195BC X-CRM114-Status: GOOD ( 21.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Zijlstra , Catalin Marinas , Jiri Olsa , Will Deacon , Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , huawei.libin@huawei.com, guohanjun@huawei.com, Namhyung Kim , liwei391@huawei.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01/04/2019 09:02, Mark Rutland wrote: > On Thu, Mar 28, 2019 at 09:49:05AM +0000, Julien Thierry wrote: >> Perf events using the dedicated cycle counter do not need to program the >> event type, the counter only ever counts that kind of events. > > Good catch! > >> Even worse, trying to program an event type without excluding the >> cycle counter index might end up in the modification of the type of >> event counted by another perf event. > > IIUC, we shouldn't affect an unrelated event. The ARM ARM says: > > When PMSELR_EL0.SEL == 31, this register accesses PMCCFILTR_EL0. > Ah yes, I missed that fact. > ... and AFAICT we program PMSELR_EL0 appropriately to select the cycle counter. > > I think we're erroneously programming the RES0 bits of PMCCFILTR_EL0, but we're > also relying on this write to clear all the filter controls in the high bits of > PMCCFILTR_EL0, which otherwise reset to UNKNOWN values. > > Given that, I think we also need to explicitly reset PMCCFILTR_EL0 in > armv8pmu_reset(). > I just realized that for the PMCCFILTR_EL0 there is also the exclude control bits for the event. Do those not need to be set when we enable the event rather than on reset? Now, I'm thinking what we need is to use a different mask than EVTYPE_MASK (one that excludes the event bits) when setting PMCCFILTR_EL0, but still do that when enabling an event using the cycle counter. Does that approach sound correct? Or am I missing something that would allow us to only set that upon reset? Thanks, > Thanks, > Mark. > >> >> Reported-by: Wei Li >> Signed-off-by: Julien Thierry >> Cc: Will Deacon >> Cc: Mark Rutland >> Cc: Catalin Marinas >> Cc: Peter Zijlstra >> Cc: Ingo Molnar >> Cc: Arnaldo Carvalho de Melo >> Cc: Alexander Shishkin >> Cc: Jiri Olsa >> Cc: Namhyung Kim >> --- >> arch/arm64/kernel/perf_event.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c >> index 4addb38..3f898bc 100644 >> --- a/arch/arm64/kernel/perf_event.c >> +++ b/arch/arm64/kernel/perf_event.c >> @@ -514,7 +514,7 @@ static inline void armv8pmu_write_event_type(struct perf_event *event) >> >> armv8pmu_write_evtype(idx - 1, hwc->config_base); >> armv8pmu_write_evtype(idx, chain_evt); >> - } else { >> + } else if (idx != ARMV8_IDX_CYCLE_COUNTER) { >> armv8pmu_write_evtype(idx, hwc->config_base); >> } >> } >> -- >> 1.9.1 -- Julien Thierry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel