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The two GPIO controller instances in the > MAIN domain share physical pins, and the vgpio_sel field routes each > pin to either bank 0 or bank 2, enabling GPIO partitioning between > software domains as documented in Technical Reference Manual[1]. The > pad configuration register field description can be referenced at [2]. > > [1] AM62L TRM (section 10.6): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf > [2] AM62L TRM (section 14.2.1.2.1): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf > > Signed-off-by: Akashdeep Kaur > --- > arch/arm64/boot/dts/ti/k3-pinctrl.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h > index 4491898d8294..d42c466fcc7b 100644 > --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h > +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h > @@ -3,11 +3,12 @@ > * This header provides constants for pinctrl bindings for TI's K3 SoC > * family. > * > - * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ > + * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/ > */ > #ifndef DTS_ARM64_TI_K3_PINCTRL_H > #define DTS_ARM64_TI_K3_PINCTRL_H > > +#define VGPIO_SEL_SHIFT (4) > #define WKUP_LVL_EN_SHIFT (7) > #define WKUP_LVL_POL_SHIFT (8) > #define DEBOUNCE_SHIFT (11) > @@ -111,6 +112,9 @@ > #define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) > #define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) > > +#define PIN_VGPIO_SEL0 (0 << VGPIO_SEL_SHIFT) > +#define PIN_VGPIO_SEL2 (1 << VGPIO_SEL_SHIFT) > + Unfortunately, this field has different meaning in different SoCs. Here is the definition from J784s4: Note this field is irrelevant when Muxmode is not 7. for MAIN GPIO 00 = GPIO0 or 1 depending on the specific pin (meaning if mode 7 has GPIO0.x then it is GPIO0 and if GPIO1.x then GPIO1) 01 - GPIO2 or 3 depending on the specific pin (meaning if mode 7 has GPIO0.x then it is GPIO2 and if GPIO1.x then GPIO3) 10 - GPIO4 or 5 depending on the specific pin (meaning if mode 7 has GPIO0.x then it is GPIO4 and if GPIO1.x then GPIO5) 11 - GPIO6 or 7 depending on the specific pin (meaning if mode 7 has GPIO0.x then it is GPIO6 and if GPIO1.x then GPIO7) Note this field is irrelevant when Muxmode is not 7. Thus, macros need to be generic or it should just open code the constant. > /* Default mux configuration for gpio-ranges to use with pinctrl */ > #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) > -- Regards Vignesh https://ti.com/opensource