[PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Ao Xu via B4 Relay]

This patch series adds DRM support for the Amlogic S4-series SoCs.
Compared to the Amlogic G12-series, the S4-series introduces the following changes:

1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
  As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
2 The S4-series secures access to HDMITX DWC and TOP registers,
  requiring modifications to the driver to handle this new access method.
3 The register addresses for the video1 and video2 planes have been updated in the S4 hardware,
  and the DRM driver has been adapted accordingly.
4 The OSD, VIU, and VPP components remain unchanged and are consistent with the G12-series.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
Ao Xu (11):
      dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller
      dt-bindings: display: meson-vpu: Add compatible for S4 display controller
      drm: meson: add S4 compatible for DRM driver
      drm: meson: add primary and overlay plane support for S4
      drm: meson: update VIU and VPP support for S4
      drm: meson: add meson_dw_hdmi support for S4
      drm: meson: change api call parameter
      drm: meson: add hdmitx vmode timing support for S4
      drm: meson: add vpu clk setting for S4
      drm: meson: add CVBS support for S4
      arm64: dts: amlogic: s4: add DRM support [1/1]

 .../bindings/display/amlogic,meson-dw-hdmi.yaml    |    1 +
 .../bindings/display/amlogic,meson-vpu.yaml        |   48 +-
 .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts     |   39 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |  121 +++
 drivers/gpu/drm/meson/meson_crtc.c                 |   90 +-
 drivers/gpu/drm/meson/meson_drv.c                  |  127 ++-
 drivers/gpu/drm/meson/meson_drv.h                  |    6 +
 drivers/gpu/drm/meson/meson_dw_hdmi.c              |  244 ++++-
 drivers/gpu/drm/meson/meson_dw_hdmi.h              |  126 +++
 drivers/gpu/drm/meson/meson_encoder_cvbs.c         |   10 +
 drivers/gpu/drm/meson/meson_encoder_hdmi.c         |   19 +-
 drivers/gpu/drm/meson/meson_overlay.c              |    7 +-
 drivers/gpu/drm/meson/meson_plane.c                |   24 +-
 drivers/gpu/drm/meson/meson_registers.h            |   17 +
 drivers/gpu/drm/meson/meson_vclk.c                 | 1018 ++++++++++++++------
 drivers/gpu/drm/meson/meson_venc.c                 |  346 ++++++-
 drivers/gpu/drm/meson/meson_venc.h                 |    4 +-
 drivers/gpu/drm/meson/meson_viu.c                  |    9 +-
 drivers/gpu/drm/meson/meson_vpp.c                  |   12 +-
 19 files changed, 1865 insertions(+), 403 deletions(-)
---
base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
change-id: 20250110-drm-s4-c96c88be52e4

Best regards,
-- 
Ao Xu <ao.xu@amlogic.com>

[PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add devicetree document for S4 HDMI controller

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
--- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -55,6 +55,7 @@ properties:
           - const: amlogic,meson-gx-dw-hdmi
       - enum:
           - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
+          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
 
   reg:
     maxItems: 1

-- 
2.43.0

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Krzysztof Kozlowski]

On Fri, Jan 10, 2025 at 01:39:51PM +0800, Ao Xu wrote:
> Add devicetree document for S4 HDMI controller
> 
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
>  Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> @@ -55,6 +55,7 @@ properties:
>            - const: amlogic,meson-gx-dw-hdmi
>        - enum:
>            - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)

Judging by of_device_id table this is compatible, so use proper
fallbacks or explain in commit msg why not.

Best regards,
Krzysztof

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Piotr Oniszczuk]

Ao,

Is there any chance to get this s4 drm hdmi series for current 6.18?

(i tried backport this series to 6.18 but have some issues with reparent vpu_0_sel to sysclk_b_sel)
   


> Wiadomość napisana przez Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> w dniu 10 sty 2025, o godz. 06:39:
> 
> From: Ao Xu <ao.xu@amlogic.com>
> 
> Add devicetree document for S4 HDMI controller
> 
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
> Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
> 1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
> @@ -55,6 +55,7 @@ properties:
>           - const: amlogic,meson-gx-dw-hdmi
>       - enum:
>           - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
> 
>   reg:
>     maxItems: 1
> 
> -- 
> 2.43.0
> 
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Chuan Liu]

Hi Piotr,


On 11/18/2025 10:50 PM, Piotr Oniszczuk wrote:
> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> [ EXTERNAL EMAIL ]
> 
> Ao,
> 
> Is there any chance to get this s4 drm hdmi series for current 6.18?
> 
> (i tried backport this series to 6.18 but have some issues with reparent vpu_0_sel to sysclk_b_sel)

Why do we need to reparent vpu_0_sel to sysclk_b_sel? is there any
background here?

The vpu_clk on S4 doesn't support sysclk_b_sel as one of its
selectable clock sources, so this reparent operation will definitely
fail. This has nothing to do with the kernel version.

> 
> 
> 
>> Wiadomość napisana przez Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> w dniu 10 sty 2025, o godz. 06:39:
>>
>> From: Ao Xu <ao.xu@amlogic.com>
>>
>> Add devicetree document for S4 HDMI controller
>>
>> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
>> ---
>> Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
>> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>> @@ -55,6 +55,7 @@ properties:
>>            - const: amlogic,meson-gx-dw-hdmi
>>        - enum:
>>            - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
>> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
>>
>>    reg:
>>      maxItems: 1
>>
>> --
>> 2.43.0
>>
>>
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Piotr Oniszczuk]

Pls see inline

> Wiadomość napisana przez Chuan Liu <chuan.liu@amlogic.com> w dniu 19 lis 2025, o godz. 03:57:
> 
> Hi Piotr,
> 
> 
> On 11/18/2025 10:50 PM, Piotr Oniszczuk wrote:
>> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>> [ EXTERNAL EMAIL ]
>> Ao,
>> Is there any chance to get this s4 drm hdmi series for current 6.18?
>> (i tried backport this series to 6.18 but have some issues with reparent vpu_0_sel to sysclk_b_sel)
> 
> Why do we need to reparent vpu_0_sel to sysclk_b_sel? is there any
> background here?

Well - it looks it is because bug....
Martin Blumenstingl had perfect eye and catch typo in patch https://lore.kernel.org/all/20250110-drm-s4-v1-11-cbc2d5edaae8@amlogic.com/:

By replacing:
assigned-clock-parents = <&clkc_periphs CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc_periphs CLKID_VPU_0>,
<&clkc_periphs CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc_periphs CLKID_VAPB_0>;

with:
assigned-clock-parents = <&clkc_pll CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc_periphs CLKID_VPU_0>,
<&clkc_pll CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc_periphs CLKID_VAPB_0>;

dmesg is like this https://termbin.com/6020

So i'm getting hdmi working - but only when device boots _without_ connected hdmi at boot (and connected later)
If hdmi is connected at boot - boot hangs at:

    0.341676] meson-dw-hdmi fe300000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
[    0.342750] meson-dw-hdmi fe300000.hdmi-tx: registered DesignWare HDMI I2C bus driver
[    0.343660] meson-drm ff000000.vpu: bound fe300000.hdmi-tx (ops meson_dw_hdmi_ops)
[    0.344832] [drm] Initialized meson 1.0.0 for ff000000.vpu on minor 0

FYI: It is after applying https://patchwork.kernel.org/project/linux-amlogic/cover/20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com/ on mainline 6.18 (with some my adjustments on this series required by changes in 6.18). 
For VPU clk changes see https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-6.18/files/0312-drm-meson-add-vpu-clk-setting-for-S4.patch 
It is 6.18 adaptation of https://patchwork.kernel.org/project/linux-amlogic/patch/20250110-drm-s4-v1-9-cbc2d5edaae8@amlogic.com/

As kernel hangs - i have limited caps to drill where root cause is. 
  
Maybe above hang is reason of my backports or missing any pre-req required to get s4 drm working?
Anyway - it will be good to test with updated to 6.18 series of Add DRM support for Amlogic S4 (plus info about any pre-req required to get s4 drm working)   
     

> 
> The vpu_clk on S4 doesn't support sysclk_b_sel as one of its
> selectable clock sources, so this reparent operation will definitely
> fail. This has nothing to do with the kernel version.
> 
>>> Wiadomość napisana przez Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> w dniu 10 sty 2025, o godz. 06:39:
>>> 
>>> From: Ao Xu <ao.xu@amlogic.com>
>>> 
>>> Add devicetree document for S4 HDMI controller
>>> 
>>> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
>>> ---
>>> Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>> 
>>> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
>>> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>> @@ -55,6 +55,7 @@ properties:
>>>           - const: amlogic,meson-gx-dw-hdmi
>>>       - enum:
>>>           - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
>>> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
>>> 
>>>   reg:
>>>     maxItems: 1
>>> 
>>> --
>>> 2.43.0
>>> 
>>> 
>>> 
>>> _______________________________________________
>>> linux-amlogic mailing list
>>> linux-amlogic@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Ao Xu]

Hi Piotr，

     I will check this issue

在 2025/11/19 18:27, Piotr Oniszczuk 写道:
> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> [ EXTERNAL EMAIL ]
>
> Pls see inline
>
>> Wiadomość napisana przez Chuan Liu <chuan.liu@amlogic.com> w dniu 19 lis 2025, o godz. 03:57:
>>
>> Hi Piotr,
>>
>>
>> On 11/18/2025 10:50 PM, Piotr Oniszczuk wrote:
>>> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>> [ EXTERNAL EMAIL ]
>>> Ao,
>>> Is there any chance to get this s4 drm hdmi series for current 6.18?
>>> (i tried backport this series to 6.18 but have some issues with reparent vpu_0_sel to sysclk_b_sel)
>> Why do we need to reparent vpu_0_sel to sysclk_b_sel? is there any
>> background here?
> Well - it looks it is because bug....
> Martin Blumenstingl had perfect eye and catch typo in patch https://lore.kernel.org/all/20250110-drm-s4-v1-11-cbc2d5edaae8@amlogic.com/:
>
> By replacing:
> assigned-clock-parents = <&clkc_periphs CLKID_FCLK_DIV3>,
> <0>, /* Do Nothing */
> <&clkc_periphs CLKID_VPU_0>,
> <&clkc_periphs CLKID_FCLK_DIV4>,
> <0>, /* Do Nothing */
> <&clkc_periphs CLKID_VAPB_0>;
>
> with:
> assigned-clock-parents = <&clkc_pll CLKID_FCLK_DIV3>,
> <0>, /* Do Nothing */
> <&clkc_periphs CLKID_VPU_0>,
> <&clkc_pll CLKID_FCLK_DIV4>,
> <0>, /* Do Nothing */
> <&clkc_periphs CLKID_VAPB_0>;
>
> dmesg is like this https://termbin.com/6020
>
> So i'm getting hdmi working - but only when device boots _without_ connected hdmi at boot (and connected later)
> If hdmi is connected at boot - boot hangs at:
>
>      0.341676] meson-dw-hdmi fe300000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
> [    0.342750] meson-dw-hdmi fe300000.hdmi-tx: registered DesignWare HDMI I2C bus driver
> [    0.343660] meson-drm ff000000.vpu: bound fe300000.hdmi-tx (ops meson_dw_hdmi_ops)
> [    0.344832] [drm] Initialized meson 1.0.0 for ff000000.vpu on minor 0
>
> FYI: It is after applying https://patchwork.kernel.org/project/linux-amlogic/cover/20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com/ on mainline 6.18 (with some my adjustments on this series required by changes in 6.18).
> For VPU clk changes see https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-6.18/files/0312-drm-meson-add-vpu-clk-setting-for-S4.patch
> It is 6.18 adaptation of https://patchwork.kernel.org/project/linux-amlogic/patch/20250110-drm-s4-v1-9-cbc2d5edaae8@amlogic.com/
>
> As kernel hangs - i have limited caps to drill where root cause is.
>
> Maybe above hang is reason of my backports or missing any pre-req required to get s4 drm working?
> Anyway - it will be good to test with updated to 6.18 series of Add DRM support for Amlogic S4 (plus info about any pre-req required to get s4 drm working)
>
>
>> The vpu_clk on S4 doesn't support sysclk_b_sel as one of its
>> selectable clock sources, so this reparent operation will definitely
>> fail. This has nothing to do with the kernel version.
>>
>>>> Wiadomość napisana przez Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> w dniu 10 sty 2025, o godz. 06:39:
>>>>
>>>> From: Ao Xu <ao.xu@amlogic.com>
>>>>
>>>> Add devicetree document for S4 HDMI controller
>>>>
>>>> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
>>>> ---
>>>> Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
>>>> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>> @@ -55,6 +55,7 @@ properties:
>>>>            - const: amlogic,meson-gx-dw-hdmi
>>>>        - enum:
>>>>            - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
>>>> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
>>>>
>>>>    reg:
>>>>      maxItems: 1
>>>>
>>>> --
>>>> 2.43.0
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-amlogic mailing list
>>>> linux-amlogic@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>> _______________________________________________
>>> linux-amlogic mailing list
>>> linux-amlogic@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller

[Piotr Oniszczuk]

Thx!

btw: i found that enabling CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER

results with: 
-no anymore boot hang on s4 (with connected hdmi)
-still black screen at s4 boot (with connected hdmi)   
-breaks boot-splash for me on other platforms (allwinner, rockchip)

maybe s4 drm series i'm using is not ready for 6.18 change of fbdev framework to DRM?
    
> Wiadomość napisana przez Ao Xu <ao.xu@amlogic.com> w dniu 21 lis 2025, o godz. 03:55:
> 
> Hi Piotr，
> 
>     I will check this issue
> 
> 在 2025/11/19 18:27, Piotr Oniszczuk 写道:
>> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>> 
>> [ EXTERNAL EMAIL ]
>> 
>> Pls see inline
>> 
>>> Wiadomość napisana przez Chuan Liu <chuan.liu@amlogic.com> w dniu 19 lis 2025, o godz. 03:57:
>>> 
>>> Hi Piotr,
>>> 
>>> 
>>> On 11/18/2025 10:50 PM, Piotr Oniszczuk wrote:
>>>> [You don't often get email from piotr.oniszczuk@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>> [ EXTERNAL EMAIL ]
>>>> Ao,
>>>> Is there any chance to get this s4 drm hdmi series for current 6.18?
>>>> (i tried backport this series to 6.18 but have some issues with reparent vpu_0_sel to sysclk_b_sel)
>>> Why do we need to reparent vpu_0_sel to sysclk_b_sel? is there any
>>> background here?
>> Well - it looks it is because bug....
>> Martin Blumenstingl had perfect eye and catch typo in patch https://lore.kernel.org/all/20250110-drm-s4-v1-11-cbc2d5edaae8@amlogic.com/:
>> 
>> By replacing:
>> assigned-clock-parents = <&clkc_periphs CLKID_FCLK_DIV3>,
>> <0>, /* Do Nothing */
>> <&clkc_periphs CLKID_VPU_0>,
>> <&clkc_periphs CLKID_FCLK_DIV4>,
>> <0>, /* Do Nothing */
>> <&clkc_periphs CLKID_VAPB_0>;
>> 
>> with:
>> assigned-clock-parents = <&clkc_pll CLKID_FCLK_DIV3>,
>> <0>, /* Do Nothing */
>> <&clkc_periphs CLKID_VPU_0>,
>> <&clkc_pll CLKID_FCLK_DIV4>,
>> <0>, /* Do Nothing */
>> <&clkc_periphs CLKID_VAPB_0>;
>> 
>> dmesg is like this https://termbin.com/6020
>> 
>> So i'm getting hdmi working - but only when device boots _without_ connected hdmi at boot (and connected later)
>> If hdmi is connected at boot - boot hangs at:
>> 
>>     0.341676] meson-dw-hdmi fe300000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
>> [    0.342750] meson-dw-hdmi fe300000.hdmi-tx: registered DesignWare HDMI I2C bus driver
>> [    0.343660] meson-drm ff000000.vpu: bound fe300000.hdmi-tx (ops meson_dw_hdmi_ops)
>> [    0.344832] [drm] Initialized meson 1.0.0 for ff000000.vpu on minor 0
>> 
>> FYI: It is after applying https://patchwork.kernel.org/project/linux-amlogic/cover/20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com/ on mainline 6.18 (with some my adjustments on this series required by changes in 6.18).
>> For VPU clk changes see https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-6.18/files/0312-drm-meson-add-vpu-clk-setting-for-S4.patch
>> It is 6.18 adaptation of https://patchwork.kernel.org/project/linux-amlogic/patch/20250110-drm-s4-v1-9-cbc2d5edaae8@amlogic.com/
>> 
>> As kernel hangs - i have limited caps to drill where root cause is.
>> 
>> Maybe above hang is reason of my backports or missing any pre-req required to get s4 drm working?
>> Anyway - it will be good to test with updated to 6.18 series of Add DRM support for Amlogic S4 (plus info about any pre-req required to get s4 drm working)
>> 
>> 
>>> The vpu_clk on S4 doesn't support sysclk_b_sel as one of its
>>> selectable clock sources, so this reparent operation will definitely
>>> fail. This has nothing to do with the kernel version.
>>> 
>>>>> Wiadomość napisana przez Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> w dniu 10 sty 2025, o godz. 06:39:
>>>>> 
>>>>> From: Ao Xu <ao.xu@amlogic.com>
>>>>> 
>>>>> Add devicetree document for S4 HDMI controller
>>>>> 
>>>>> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
>>>>> ---
>>>>> Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>> 
>>>>> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>>> index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450a6c40e08def38 100644
>>>>> --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
>>>>> @@ -55,6 +55,7 @@ properties:
>>>>>           - const: amlogic,meson-gx-dw-hdmi
>>>>>       - enum:
>>>>>           - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
>>>>> +          - amlogic,meson-s4-dw-hdmi # S4 (S905Y4)
>>>>> 
>>>>>   reg:
>>>>>     maxItems: 1
>>>>> 
>>>>> --
>>>>> 2.43.0
>>>>> 
>>>>> 
>>>>> 
>>>>> _______________________________________________
>>>>> linux-amlogic mailing list
>>>>> linux-amlogic@lists.infradead.org
>>>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>>> _______________________________________________
>>>> linux-amlogic mailing list
>>>> linux-amlogic@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH 02/11] dt-bindings: display: meson-vpu: Add compatible for S4 display controller

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add devicetree document for S4 VPU

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 .../bindings/display/amlogic,meson-vpu.yaml        | 48 ++++++++++++++++++++--
 1 file changed, 44 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
index cb0a90f0232190031430c08f936b8f0d3b217601..3d7eceb3724e81d9c911039507df072d332a028f 100644
--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
@@ -66,14 +66,13 @@ properties:
           - const: amlogic,meson-gx-vpu
       - enum:
           - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
+          - amlogic,meson-s4-vpu # S4 (S905Y4)
 
   reg:
-    maxItems: 2
+    minItems: 2
 
   reg-names:
-    items:
-      - const: vpu
-      - const: hhi
+    minItems: 2
 
   interrupts:
     maxItems: 1
@@ -117,6 +116,47 @@ required:
   - "#size-cells"
   - amlogic,canvas
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: amlogic,meson-s4-vpu
+    then:
+      properties:
+        reg:
+          items:
+            - description: vcbus registers
+            - description: hhi registers
+            - description: clkctrl registers
+            - description: power control registers
+            - description: sysctrl registers
+        reg-names:
+          items:
+            - const: vpu
+            - const: hhi
+            - const: clkctrl
+            - const: pwctrl
+            - const: sysctrl
+        clocks:
+          items:
+            - description: vpu clock
+            - description: vapb clock
+        clock-names:
+          items:
+            - const: vpu
+            - const: vapb
+    else:
+      properties:
+        reg:
+          items:
+            - description: vcbus registers
+            - description: hhi registers
+        reg-names:
+          items:
+            - const: vpu
+            - const: hhi
+
 additionalProperties: false
 
 examples:

-- 
2.43.0

Re: [PATCH 02/11] dt-bindings: display: meson-vpu: Add compatible for S4 display controller

[Krzysztof Kozlowski]

On 10/01/2025 06:39, Ao Xu via B4 Relay wrote:
> From: Ao Xu <ao.xu@amlogic.com>
> 
> Add devicetree document for S4 VPU
> 
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
>  .../bindings/display/amlogic,meson-vpu.yaml        | 48 ++++++++++++++++++++--
>  1 file changed, 44 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> index cb0a90f0232190031430c08f936b8f0d3b217601..3d7eceb3724e81d9c911039507df072d332a028f 100644
> --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> @@ -66,14 +66,13 @@ properties:
>            - const: amlogic,meson-gx-vpu
>        - enum:
>            - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
> +          - amlogic,meson-s4-vpu # S4 (S905Y4)
>  
>    reg:
> -    maxItems: 2
> +    minItems: 2

Missing maxItems

>  
>    reg-names:
> -    items:
> -      - const: vpu
> -      - const: hhi
> +    minItems: 2

Just grow the list here with minItems

>  
>    interrupts:
>      maxItems: 1
> @@ -117,6 +116,47 @@ required:
>    - "#size-cells"
>    - amlogic,canvas
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: amlogic,meson-s4-vpu
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: vcbus registers
> +            - description: hhi registers
> +            - description: clkctrl registers
> +            - description: power control registers
> +            - description: sysctrl registers
> +        reg-names:
> +          items:
> +            - const: vpu
> +            - const: hhi
> +            - const: clkctrl
> +            - const: pwctrl
> +            - const: sysctrl

and here min/maxItems

> +        clocks:
> +          items:
> +            - description: vpu clock
> +            - description: vapb clock
> +        clock-names:
> +          items:
> +            - const: vpu
> +            - const: vapb

All properties must be defined in top-level. Just disallow it :false for
other variants.

> +    else:
> +      properties:
> +        reg:
> +          items:
> +            - description: vcbus registers
> +            - description: hhi registers
> +        reg-names:
> +          items:
> +            - const: vpu
> +            - const: hhi

maxItems: 2


Look how other bindings are doing it for lists with common parts.

Best regards,
Krzysztof

[PATCH 03/11] drm: meson: add S4 compatible for DRM driver

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add S4 compatible for DRM driver. This update driver logic to support
S4-specific configurations. This also add vpu clock operation in
bind, suspend, resume, shutdown stage.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_drv.c | 127 +++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/meson/meson_drv.h |   6 ++
 2 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index 81d2ee37e7732dca89d02347b9c972300b38771a..d28094efeb137ae0b9990ab3608825d563358dba 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -11,6 +11,7 @@
 #include <linux/aperture.h>
 #include <linux/component.h>
 #include <linux/module.h>
+#include <linux/clk.h>
 #include <linux/of_graph.h>
 #include <linux/sys_soc.h>
 #include <linux/platform_device.h>
@@ -160,6 +161,34 @@ static void meson_vpu_init(struct meson_drm *priv)
 	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
 }
 
+static void meson_setup_clk(struct meson_drm *priv, bool enable)
+{
+	int ret;
+
+	if (!priv || !priv->vpu_clk || !priv->vapb_clk)
+		return;
+
+	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		return;
+
+	if (enable) {
+		ret = clk_prepare_enable(priv->vpu_clk);
+		if (ret) {
+			dev_err(priv->dev, "Failed to set vpu clk\n");
+			return;
+		}
+		ret = clk_prepare_enable(priv->vapb_clk);
+		if (ret) {
+			dev_err(priv->dev, "Failed to Set vapb clk\n");
+			clk_disable_unprepare(priv->vpu_clk);
+			return;
+		}
+	} else {
+		clk_disable_unprepare(priv->vpu_clk);
+		clk_disable_unprepare(priv->vapb_clk);
+	}
+}
+
 struct meson_drm_soc_attr {
 	struct meson_drm_soc_limits limits;
 	const struct soc_device_attribute *attrs;
@@ -241,6 +270,83 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
 		goto free_drm;
 	}
 
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sysctrl");
+		if (!res) {
+			ret = -EINVAL;
+			goto free_drm;
+		}
+		/* Simply ioremap since it may be a shared register zone */
+		regs = devm_ioremap(dev, res->start, resource_size(res));
+		if (!regs) {
+			ret = -EADDRNOTAVAIL;
+			goto free_drm;
+		}
+
+		priv->sysctrl = devm_regmap_init_mmio(dev, regs,
+						  &meson_regmap_config);
+		if (IS_ERR(priv->sysctrl)) {
+			dev_err(&pdev->dev, "Couldn't create the SYSCTRL regmap\n");
+			ret = PTR_ERR(priv->sysctrl);
+			goto free_drm;
+		}
+
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clkctrl");
+		if (!res) {
+			ret = -EINVAL;
+			goto free_drm;
+		}
+		/* Simply ioremap since it may be a shared register zone */
+		regs = devm_ioremap(dev, res->start, resource_size(res));
+		if (!regs) {
+			ret = -EADDRNOTAVAIL;
+			goto free_drm;
+		}
+
+		priv->clkctrl = devm_regmap_init_mmio(dev, regs,
+						  &meson_regmap_config);
+		if (IS_ERR(priv->clkctrl)) {
+			dev_err(&pdev->dev, "Couldn't create the clkctrl regmap\n");
+			ret = PTR_ERR(priv->clkctrl);
+			goto free_drm;
+		}
+
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrctrl");
+		if (!res) {
+			ret = -EINVAL;
+			goto free_drm;
+		}
+		/* Simply ioremap since it may be a shared register zone */
+		regs = devm_ioremap(dev, res->start, resource_size(res));
+		if (!regs) {
+			ret = -EADDRNOTAVAIL;
+			goto free_drm;
+		}
+
+		priv->pwrctrl = devm_regmap_init_mmio(dev, regs,
+						  &meson_regmap_config);
+		if (IS_ERR(priv->pwrctrl)) {
+			dev_err(&pdev->dev, "Couldn't create the pwrctrl regmap\n");
+			ret = PTR_ERR(priv->pwrctrl);
+			goto free_drm;
+		}
+
+		priv->vpu_clk = devm_clk_get(&pdev->dev, "vpu");
+		if (IS_ERR(priv->vpu_clk)) {
+			dev_err(&pdev->dev, "vpu clock request failed\n");
+			ret = PTR_ERR(priv->vpu_clk);
+			goto free_drm;
+		}
+
+		priv->vapb_clk = devm_clk_get(&pdev->dev, "vapb");
+		if (IS_ERR(priv->vapb_clk)) {
+			dev_err(&pdev->dev, "vapb clock request failed\n");
+			ret = PTR_ERR(priv->vapb_clk);
+			goto free_drm;
+		}
+		meson_setup_clk(priv, true);
+	}
+
 	priv->canvas = meson_canvas_get(dev);
 	if (IS_ERR(priv->canvas)) {
 		ret = PTR_ERR(priv->canvas);
@@ -424,12 +530,21 @@ static const struct component_master_ops meson_drv_master_ops = {
 
 static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
 {
+	int ret;
 	struct meson_drm *priv = dev_get_drvdata(dev);
 
 	if (!priv)
 		return 0;
 
-	return drm_mode_config_helper_suspend(priv->drm);
+	ret = drm_mode_config_helper_suspend(priv->drm);
+	if (unlikely(ret)) {
+		drm_err(dev, "suspend error: %d", ret);
+		return ret;
+	}
+
+	meson_setup_clk(priv, false);
+
+	return ret;
 }
 
 static int __maybe_unused meson_drv_pm_resume(struct device *dev)
@@ -439,6 +554,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev)
 	if (!priv)
 		return 0;
 
+	meson_setup_clk(priv, true);
 	meson_vpu_init(priv);
 	meson_venc_init(priv);
 	meson_vpp_init(priv);
@@ -458,6 +574,7 @@ static void meson_drv_shutdown(struct platform_device *pdev)
 
 	drm_kms_helper_poll_fini(priv->drm);
 	drm_atomic_helper_shutdown(priv->drm);
+	meson_setup_clk(priv, false);
 }
 
 /*
@@ -471,6 +588,7 @@ static const struct of_device_id components_dev_match[] = {
 	{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
 	{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
 	{ .compatible = "amlogic,meson-g12a-dw-hdmi" },
+	{ .compatible = "amlogic,meson-s4-dw-hdmi" },
 	{}
 };
 
@@ -539,6 +657,11 @@ static struct meson_drm_match_data meson_drm_g12a_data = {
 	.afbcd_ops = &meson_afbcd_g12a_ops,
 };
 
+static struct meson_drm_match_data meson_drm_s4_data = {
+	.compat = VPU_COMPATIBLE_S4,
+	.afbcd_ops = &meson_afbcd_g12a_ops,
+};
+
 static const struct of_device_id dt_match[] = {
 	{ .compatible = "amlogic,meson-gxbb-vpu",
 	  .data       = (void *)&meson_drm_gxbb_data },
@@ -548,6 +671,8 @@ static const struct of_device_id dt_match[] = {
 	  .data       = (void *)&meson_drm_gxm_data },
 	{ .compatible = "amlogic,meson-g12a-vpu",
 	  .data       = (void *)&meson_drm_g12a_data },
+	{ .compatible = "amlogic,meson-s4-vpu",
+	  .data       = (void *)&meson_drm_s4_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dt_match);
diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
index 3f9345c14f31c13b071f420533fe8a450d3e0f36..c801a2e3e55a054247710aebae5602e44c9e1624 100644
--- a/drivers/gpu/drm/meson/meson_drv.h
+++ b/drivers/gpu/drm/meson/meson_drv.h
@@ -22,6 +22,7 @@ enum vpu_compatible {
 	VPU_COMPATIBLE_GXL  = 1,
 	VPU_COMPATIBLE_GXM  = 2,
 	VPU_COMPATIBLE_G12A = 3,
+	VPU_COMPATIBLE_S4 = 4,
 };
 
 enum {
@@ -45,6 +46,11 @@ struct meson_drm {
 	enum vpu_compatible compat;
 	void __iomem *io_base;
 	struct regmap *hhi;
+	struct regmap *sysctrl;
+	struct regmap *clkctrl;
+	struct regmap *pwrctrl;
+	struct clk *vpu_clk;
+	struct clk *vapb_clk;
 	int vsync_irq;
 
 	struct meson_canvas *canvas;

-- 
2.43.0

Re: [PATCH 03/11] drm: meson: add S4 compatible for DRM driver

[Jerome Brunet]

On Fri 10 Jan 2025 at 13:39, Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org> wrote:

> From: Ao Xu <ao.xu@amlogic.com>
>
> Add S4 compatible for DRM driver. This update driver logic to support
> S4-specific configurations. This also add vpu clock operation in
> bind, suspend, resume, shutdown stage.
>
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
>  drivers/gpu/drm/meson/meson_drv.c | 127 +++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/meson/meson_drv.h |   6 ++
>  2 files changed, 132 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
> index 81d2ee37e7732dca89d02347b9c972300b38771a..d28094efeb137ae0b9990ab3608825d563358dba 100644
> --- a/drivers/gpu/drm/meson/meson_drv.c
> +++ b/drivers/gpu/drm/meson/meson_drv.c
> @@ -11,6 +11,7 @@
>  #include <linux/aperture.h>
>  #include <linux/component.h>
>  #include <linux/module.h>
> +#include <linux/clk.h>
>  #include <linux/of_graph.h>
>  #include <linux/sys_soc.h>
>  #include <linux/platform_device.h>
> @@ -160,6 +161,34 @@ static void meson_vpu_init(struct meson_drm *priv)
>  	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
>  }
>  
> +static void meson_setup_clk(struct meson_drm *priv, bool enable)
> +{
> +	int ret;
> +
> +	if (!priv || !priv->vpu_clk || !priv->vapb_clk)
> +		return;
> +
> +	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
> +		return;
> +
> +	if (enable) {
> +		ret = clk_prepare_enable(priv->vpu_clk);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to set vpu clk\n");
> +			return;
> +		}
> +		ret = clk_prepare_enable(priv->vapb_clk);
> +		if (ret) {
> +			dev_err(priv->dev, "Failed to Set vapb clk\n");
> +			clk_disable_unprepare(priv->vpu_clk);
> +			return;
> +		}
> +	} else {
> +		clk_disable_unprepare(priv->vpu_clk);
> +		clk_disable_unprepare(priv->vapb_clk);
> +	}
> +}
> +
>  struct meson_drm_soc_attr {
>  	struct meson_drm_soc_limits limits;
>  	const struct soc_device_attribute *attrs;
> @@ -241,6 +270,83 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
>  		goto free_drm;
>  	}
>  
> +	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sysctrl");
> +		if (!res) {
> +			ret = -EINVAL;
> +			goto free_drm;
> +		}
> +		/* Simply ioremap since it may be a shared register zone */

This comment, the name of the zone and even the usage you are making of
it clearly show this is repeating the error of past, directly accessing
improperly shared registers which should otherwise have been implemented
as proper controller using the kernel available framework, such PD, phys,
clock, reset, etc ...

Worse, it gets encoded into the dt binding, making extremely difficult
to fix later on.

> +		regs = devm_ioremap(dev, res->start, resource_size(res));
> +		if (!regs) {
> +			ret = -EADDRNOTAVAIL;
> +			goto free_drm;
> +		}
> +
> +		priv->sysctrl = devm_regmap_init_mmio(dev, regs,
> +						  &meson_regmap_config);
> +		if (IS_ERR(priv->sysctrl)) {
> +			dev_err(&pdev->dev, "Couldn't create the SYSCTRL regmap\n");
> +			ret = PTR_ERR(priv->sysctrl);
> +			goto free_drm;
> +		}
> +
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clkctrl");
> +		if (!res) {
> +			ret = -EINVAL;
> +			goto free_drm;
> +		}
> +		/* Simply ioremap since it may be a shared register zone */
> +		regs = devm_ioremap(dev, res->start, resource_size(res));
> +		if (!regs) {
> +			ret = -EADDRNOTAVAIL;
> +			goto free_drm;
> +		}
> +
> +		priv->clkctrl = devm_regmap_init_mmio(dev, regs,
> +						  &meson_regmap_config);
> +		if (IS_ERR(priv->clkctrl)) {
> +			dev_err(&pdev->dev, "Couldn't create the clkctrl regmap\n");
> +			ret = PTR_ERR(priv->clkctrl);
> +			goto free_drm;
> +		}
> +
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrctrl");
> +		if (!res) {
> +			ret = -EINVAL;
> +			goto free_drm;
> +		}
> +		/* Simply ioremap since it may be a shared register zone */
> +		regs = devm_ioremap(dev, res->start, resource_size(res));
> +		if (!regs) {
> +			ret = -EADDRNOTAVAIL;
> +			goto free_drm;
> +		}
> +
> +		priv->pwrctrl = devm_regmap_init_mmio(dev, regs,
> +						  &meson_regmap_config);
> +		if (IS_ERR(priv->pwrctrl)) {
> +			dev_err(&pdev->dev, "Couldn't create the pwrctrl regmap\n");
> +			ret = PTR_ERR(priv->pwrctrl);
> +			goto free_drm;
> +		}
> +
> +		priv->vpu_clk = devm_clk_get(&pdev->dev, "vpu");
> +		if (IS_ERR(priv->vpu_clk)) {
> +			dev_err(&pdev->dev, "vpu clock request failed\n");
> +			ret = PTR_ERR(priv->vpu_clk);
> +			goto free_drm;
> +		}
> +
> +		priv->vapb_clk = devm_clk_get(&pdev->dev, "vapb");
> +		if (IS_ERR(priv->vapb_clk)) {
> +			dev_err(&pdev->dev, "vapb clock request failed\n");
> +			ret = PTR_ERR(priv->vapb_clk);
> +			goto free_drm;
> +		}
> +		meson_setup_clk(priv, true);
> +	}
> +
>  	priv->canvas = meson_canvas_get(dev);
>  	if (IS_ERR(priv->canvas)) {
>  		ret = PTR_ERR(priv->canvas);
> @@ -424,12 +530,21 @@ static const struct component_master_ops meson_drv_master_ops = {
>  
>  static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
>  {
> +	int ret;
>  	struct meson_drm *priv = dev_get_drvdata(dev);
>  
>  	if (!priv)
>  		return 0;
>  
> -	return drm_mode_config_helper_suspend(priv->drm);
> +	ret = drm_mode_config_helper_suspend(priv->drm);
> +	if (unlikely(ret)) {
> +		drm_err(dev, "suspend error: %d", ret);
> +		return ret;
> +	}
> +
> +	meson_setup_clk(priv, false);
> +
> +	return ret;
>  }
>  
>  static int __maybe_unused meson_drv_pm_resume(struct device *dev)
> @@ -439,6 +554,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev)
>  	if (!priv)
>  		return 0;
>  
> +	meson_setup_clk(priv, true);
>  	meson_vpu_init(priv);
>  	meson_venc_init(priv);
>  	meson_vpp_init(priv);
> @@ -458,6 +574,7 @@ static void meson_drv_shutdown(struct platform_device *pdev)
>  
>  	drm_kms_helper_poll_fini(priv->drm);
>  	drm_atomic_helper_shutdown(priv->drm);
> +	meson_setup_clk(priv, false);
>  }
>  
>  /*
> @@ -471,6 +588,7 @@ static const struct of_device_id components_dev_match[] = {
>  	{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
>  	{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
>  	{ .compatible = "amlogic,meson-g12a-dw-hdmi" },
> +	{ .compatible = "amlogic,meson-s4-dw-hdmi" },
>  	{}
>  };
>  
> @@ -539,6 +657,11 @@ static struct meson_drm_match_data meson_drm_g12a_data = {
>  	.afbcd_ops = &meson_afbcd_g12a_ops,
>  };
>  
> +static struct meson_drm_match_data meson_drm_s4_data = {
> +	.compat = VPU_COMPATIBLE_S4,
> +	.afbcd_ops = &meson_afbcd_g12a_ops,
> +};
> +
>  static const struct of_device_id dt_match[] = {
>  	{ .compatible = "amlogic,meson-gxbb-vpu",
>  	  .data       = (void *)&meson_drm_gxbb_data },
> @@ -548,6 +671,8 @@ static const struct of_device_id dt_match[] = {
>  	  .data       = (void *)&meson_drm_gxm_data },
>  	{ .compatible = "amlogic,meson-g12a-vpu",
>  	  .data       = (void *)&meson_drm_g12a_data },
> +	{ .compatible = "amlogic,meson-s4-vpu",
> +	  .data       = (void *)&meson_drm_s4_data },
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, dt_match);
> diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
> index 3f9345c14f31c13b071f420533fe8a450d3e0f36..c801a2e3e55a054247710aebae5602e44c9e1624 100644
> --- a/drivers/gpu/drm/meson/meson_drv.h
> +++ b/drivers/gpu/drm/meson/meson_drv.h
> @@ -22,6 +22,7 @@ enum vpu_compatible {
>  	VPU_COMPATIBLE_GXL  = 1,
>  	VPU_COMPATIBLE_GXM  = 2,
>  	VPU_COMPATIBLE_G12A = 3,
> +	VPU_COMPATIBLE_S4 = 4,
>  };
>  
>  enum {
> @@ -45,6 +46,11 @@ struct meson_drm {
>  	enum vpu_compatible compat;
>  	void __iomem *io_base;
>  	struct regmap *hhi;
> +	struct regmap *sysctrl;
> +	struct regmap *clkctrl;
> +	struct regmap *pwrctrl;
> +	struct clk *vpu_clk;
> +	struct clk *vapb_clk;
>  	int vsync_irq;
>  
>  	struct meson_canvas *canvas;

-- 
Jerome

Re: [PATCH 03/11] drm: meson: add S4 compatible for DRM driver

[kernel test robot]

Hi Ao,

kernel test robot noticed the following build errors:

[auto build test ERROR on 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab]

url:    https://github.com/intel-lab-lkp/linux/commits/Ao-Xu-via-B4-Relay/dt-bindings-display-meson-dw-hdmi-Add-compatible-for-S4-HDMI-controller/20250110-134113
base:   6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
patch link:    https://lore.kernel.org/r/20250110-drm-s4-v1-3-cbc2d5edaae8%40amlogic.com
patch subject: [PATCH 03/11] drm: meson: add S4 compatible for DRM driver
config: csky-randconfig-002-20250111 (https://download.01.org/0day-ci/archive/20250111/202501111433.iVcR3vZY-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250111/202501111433.iVcR3vZY-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501111433.iVcR3vZY-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from include/linux/device.h:15,
                    from include/linux/sys_soc.h:9,
                    from drivers/gpu/drm/meson/meson_drv.c:16:
   drivers/gpu/drm/meson/meson_drv.c: In function 'meson_drv_pm_suspend':
>> include/drm/drm_print.h:588:42: error: 'struct device' has no member named 'dev'; did you mean 'devt'?
     588 |         dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
         |                                          ^~~
   include/linux/dev_printk.h:110:25: note: in definition of macro 'dev_printk_index_wrap'
     110 |                 _p_func(dev, fmt, ##__VA_ARGS__);                       \
         |                         ^~~
   include/drm/drm_print.h:588:9: note: in expansion of macro 'dev_err'
     588 |         dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
         |         ^~~~
   include/drm/drm_print.h:601:9: note: in expansion of macro '__drm_printk'
     601 |         __drm_printk((drm), err,, "*ERROR* " fmt, ##__VA_ARGS__)
         |         ^~~~~~~~~~~~
   drivers/gpu/drm/meson/meson_drv.c:541:17: note: in expansion of macro 'drm_err'
     541 |                 drm_err(dev, "suspend error: %d", ret);
         |                 ^~~~~~~
--
   In file included from include/linux/device.h:15,
                    from include/linux/sys_soc.h:9,
                    from meson_drv.c:16:
   meson_drv.c: In function 'meson_drv_pm_suspend':
>> include/drm/drm_print.h:588:42: error: 'struct device' has no member named 'dev'; did you mean 'devt'?
     588 |         dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
         |                                          ^~~
   include/linux/dev_printk.h:110:25: note: in definition of macro 'dev_printk_index_wrap'
     110 |                 _p_func(dev, fmt, ##__VA_ARGS__);                       \
         |                         ^~~
   include/drm/drm_print.h:588:9: note: in expansion of macro 'dev_err'
     588 |         dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
         |         ^~~~
   include/drm/drm_print.h:601:9: note: in expansion of macro '__drm_printk'
     601 |         __drm_printk((drm), err,, "*ERROR* " fmt, ##__VA_ARGS__)
         |         ^~~~~~~~~~~~
   meson_drv.c:541:17: note: in expansion of macro 'drm_err'
     541 |                 drm_err(dev, "suspend error: %d", ret);
         |                 ^~~~~~~


vim +588 include/drm/drm_print.h

e820f52577b14c Jim Cromie            2022-09-11  548  
02c9656b2f0d69 Haneen Mohammed       2017-10-17  549  /**
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  550   * DRM_DEV_DEBUG() - Debug output for generic drm code
02c9656b2f0d69 Haneen Mohammed       2017-10-17  551   *
306589856399e1 Douglas Anderson      2021-09-21  552   * NOTE: this is deprecated in favor of drm_dbg_core().
306589856399e1 Douglas Anderson      2021-09-21  553   *
091756bbb1a961 Haneen Mohammed       2017-10-17  554   * @dev: device pointer
091756bbb1a961 Haneen Mohammed       2017-10-17  555   * @fmt: printf() like format string.
02c9656b2f0d69 Haneen Mohammed       2017-10-17  556   */
db87086492581c Joe Perches           2018-03-16  557  #define DRM_DEV_DEBUG(dev, fmt, ...)					\
db87086492581c Joe Perches           2018-03-16  558  	drm_dev_dbg(dev, DRM_UT_CORE, fmt, ##__VA_ARGS__)
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  559  /**
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  560   * DRM_DEV_DEBUG_DRIVER() - Debug output for vendor specific part of the driver
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  561   *
306589856399e1 Douglas Anderson      2021-09-21  562   * NOTE: this is deprecated in favor of drm_dbg() or dev_dbg().
306589856399e1 Douglas Anderson      2021-09-21  563   *
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  564   * @dev: device pointer
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  565   * @fmt: printf() like format string.
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  566   */
db87086492581c Joe Perches           2018-03-16  567  #define DRM_DEV_DEBUG_DRIVER(dev, fmt, ...)				\
db87086492581c Joe Perches           2018-03-16  568  	drm_dev_dbg(dev, DRM_UT_DRIVER,	fmt, ##__VA_ARGS__)
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  569  /**
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  570   * DRM_DEV_DEBUG_KMS() - Debug output for modesetting code
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  571   *
306589856399e1 Douglas Anderson      2021-09-21  572   * NOTE: this is deprecated in favor of drm_dbg_kms().
306589856399e1 Douglas Anderson      2021-09-21  573   *
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  574   * @dev: device pointer
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  575   * @fmt: printf() like format string.
b52817e9de06a3 Mauro Carvalho Chehab 2020-10-27  576   */
db87086492581c Joe Perches           2018-03-16  577  #define DRM_DEV_DEBUG_KMS(dev, fmt, ...)				\
db87086492581c Joe Perches           2018-03-16  578  	drm_dev_dbg(dev, DRM_UT_KMS, fmt, ##__VA_ARGS__)
a18b21929453af Lyude Paul            2018-07-16  579  
fb6c7ab8718eb2 Jani Nikula           2019-12-10  580  /*
fb6c7ab8718eb2 Jani Nikula           2019-12-10  581   * struct drm_device based logging
fb6c7ab8718eb2 Jani Nikula           2019-12-10  582   *
fb6c7ab8718eb2 Jani Nikula           2019-12-10  583   * Prefer drm_device based logging over device or prink based logging.
fb6c7ab8718eb2 Jani Nikula           2019-12-10  584   */
fb6c7ab8718eb2 Jani Nikula           2019-12-10  585  
fb6c7ab8718eb2 Jani Nikula           2019-12-10  586  /* Helper for struct drm_device based logging. */
fb6c7ab8718eb2 Jani Nikula           2019-12-10  587  #define __drm_printk(drm, level, type, fmt, ...)			\
e04d24c4e8062b Luben Tuikov          2023-11-16 @588  	dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
fb6c7ab8718eb2 Jani Nikula           2019-12-10  589  
fb6c7ab8718eb2 Jani Nikula           2019-12-10  590  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 03/11] drm: meson: add S4 compatible for DRM driver

[kernel test robot]

Hi Ao,

kernel test robot noticed the following build errors:

[auto build test ERROR on 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab]

url:    https://github.com/intel-lab-lkp/linux/commits/Ao-Xu-via-B4-Relay/dt-bindings-display-meson-dw-hdmi-Add-compatible-for-S4-HDMI-controller/20250110-134113
base:   6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
patch link:    https://lore.kernel.org/r/20250110-drm-s4-v1-3-cbc2d5edaae8%40amlogic.com
patch subject: [PATCH 03/11] drm: meson: add S4 compatible for DRM driver
config: arm64-randconfig-002-20250111 (https://download.01.org/0day-ci/archive/20250111/202501111505.wNSI9zrC-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project f5cd181ffbb7cb61d582fe130d46580d5969d47a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250111/202501111505.wNSI9zrC-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501111505.wNSI9zrC-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/meson/meson_drv.c:541:3: error: no member named 'dev' in 'struct device'; did you mean 'devt'?
     541 |                 drm_err(dev, "suspend error: %d", ret);
         |                 ^
   include/drm/drm_print.h:601:2: note: expanded from macro 'drm_err'
     601 |         __drm_printk((drm), err,, "*ERROR* " fmt, ##__VA_ARGS__)
         |         ^
   include/drm/drm_print.h:588:35: note: expanded from macro '__drm_printk'
     588 |         dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__)
         |                                          ^
   include/linux/device.h:794:10: note: 'devt' declared here
     794 |         dev_t                   devt;   /* dev_t, creates the sysfs "dev" */
         |                                 ^
   1 error generated.


vim +541 drivers/gpu/drm/meson/meson_drv.c

   530	
   531	static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
   532	{
   533		int ret;
   534		struct meson_drm *priv = dev_get_drvdata(dev);
   535	
   536		if (!priv)
   537			return 0;
   538	
   539		ret = drm_mode_config_helper_suspend(priv->drm);
   540		if (unlikely(ret)) {
 > 541			drm_err(dev, "suspend error: %d", ret);
   542			return ret;
   543		}
   544	
   545		meson_setup_clk(priv, false);
   546	
   547		return ret;
   548	}
   549	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 04/11] drm: meson: add primary and overlay plane support for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Update plane register configurations in the Meson DRM driver
to support the Amlogic S4 SoC. These adjustments ensure proper
handling of display planes with S4-specific hardware requirements.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_crtc.c      | 90 +++++++++++++++++++++++----------
 drivers/gpu/drm/meson/meson_overlay.c   |  7 ++-
 drivers/gpu/drm/meson/meson_plane.c     | 24 ++++++---
 drivers/gpu/drm/meson/meson_registers.h | 16 ++++++
 4 files changed, 102 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index d70616da8ce2fd974b57af6aadca5c98fbb88fce..64c7450b7f688d8997e8ad23947bff3ec6484aff 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -28,6 +28,7 @@
 #include "meson_osd_afbcd.h"
 
 #define MESON_G12A_VIU_OFFSET	0x5ec0
+#define MESON_S4_VIU_OFFSET	0xb6c0
 
 /* CRTC definition */
 
@@ -479,21 +480,60 @@ void meson_crtc_irq(struct meson_drm *priv)
 		writel_relaxed(priv->viu.vd1_if0_gen_reg,
 				priv->io_base + meson_crtc->viu_offset +
 				_REG(VD2_IF0_GEN_REG));
-		writel_relaxed(priv->viu.vd1_if0_gen_reg2,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VD1_IF0_GEN_REG2));
-		writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VIU_VD1_FMT_CTRL));
-		writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VIU_VD2_FMT_CTRL));
-		writel_relaxed(priv->viu.viu_vd1_fmt_w,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VIU_VD1_FMT_W));
-		writel_relaxed(priv->viu.viu_vd1_fmt_w,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VIU_VD2_FMT_W));
+
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			writel_relaxed(priv->viu.vd1_if0_gen_reg2,
+					priv->io_base +
+					_REG(VD1_IF0_GEN_REG2_S4));
+			writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
+					priv->io_base +
+					_REG(VIU_VD1_FMT_CTRL_S4));
+			writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
+					priv->io_base +
+					_REG(VIU_VD2_FMT_CTRL_S4));
+			writel_relaxed(priv->viu.viu_vd1_fmt_w,
+					priv->io_base +
+					_REG(VIU_VD1_FMT_W_S4));
+			writel_relaxed(priv->viu.viu_vd1_fmt_w,
+					priv->io_base +
+					_REG(VIU_VD2_FMT_W_S4));
+
+			writel_relaxed(priv->viu.vd1_range_map_y,
+					priv->io_base +
+					_REG(VD1_IF0_RANGE_MAP_Y_S4));
+			writel_relaxed(priv->viu.vd1_range_map_cb,
+					priv->io_base +
+					_REG(VD1_IF0_RANGE_MAP_CB_S4));
+			writel_relaxed(priv->viu.vd1_range_map_cr,
+					priv->io_base +
+					_REG(VD1_IF0_RANGE_MAP_CR_S4));
+		} else {
+			writel_relaxed(priv->viu.vd1_if0_gen_reg2,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VD1_IF0_GEN_REG2));
+			writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VIU_VD1_FMT_CTRL));
+			writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VIU_VD2_FMT_CTRL));
+			writel_relaxed(priv->viu.viu_vd1_fmt_w,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VIU_VD1_FMT_W));
+			writel_relaxed(priv->viu.viu_vd1_fmt_w,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VIU_VD2_FMT_W));
+
+			writel_relaxed(priv->viu.vd1_range_map_y,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VD1_IF0_RANGE_MAP_Y));
+			writel_relaxed(priv->viu.vd1_range_map_cb,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VD1_IF0_RANGE_MAP_CB));
+			writel_relaxed(priv->viu.vd1_range_map_cr,
+					priv->io_base + meson_crtc->viu_offset +
+					_REG(VD1_IF0_RANGE_MAP_CR));
+		}
 		writel_relaxed(priv->viu.vd1_if0_canvas0,
 				priv->io_base + meson_crtc->viu_offset +
 				_REG(VD1_IF0_CANVAS0));
@@ -592,15 +632,7 @@ void meson_crtc_irq(struct meson_drm *priv)
 				_REG(VD2_IF0_LUMA_PSEL));
 		writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
 				_REG(VD2_IF0_CHROMA_PSEL));
-		writel_relaxed(priv->viu.vd1_range_map_y,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VD1_IF0_RANGE_MAP_Y));
-		writel_relaxed(priv->viu.vd1_range_map_cb,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VD1_IF0_RANGE_MAP_CB));
-		writel_relaxed(priv->viu.vd1_range_map_cr,
-				priv->io_base + meson_crtc->viu_offset +
-				_REG(VD1_IF0_RANGE_MAP_CR));
+
 		writel_relaxed(VPP_VSC_BANK_LENGTH(4) |
 			       VPP_HSC_BANK_LENGTH(4) |
 			       VPP_SC_VD_EN_ENABLE |
@@ -692,10 +724,16 @@ int meson_crtc_create(struct meson_drm *priv)
 		return ret;
 	}
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1;
 		meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1;
-		meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET;
+
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+			meson_crtc->viu_offset = MESON_S4_VIU_OFFSET;
+		else
+			meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET;
+
 		meson_crtc->enable_osd1_afbc =
 					meson_crtc_g12a_enable_osd1_afbc;
 		meson_crtc->disable_osd1_afbc =
diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c
index 7f98de38842bf932ca3388707ec3e2f2c38d97e3..3cf2efa407849d6af9b010a5ad53e611155b6c9f 100644
--- a/drivers/gpu/drm/meson/meson_overlay.c
+++ b/drivers/gpu/drm/meson/meson_overlay.c
@@ -733,7 +733,12 @@ static void meson_overlay_atomic_disable(struct drm_plane *plane,
 	priv->viu.vd1_enabled = false;
 
 	/* Disable VD1 */
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
+		writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
+		writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x2db0));
+		writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x2db0));
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 		writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
 		writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
 		writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index b43ac61201f3123e58effa9c4b734c23cfd3d5df..79cfa42af00f34f23993ab4b7af8b7bdfb23abce 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -161,7 +161,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
 
 	/* Check if AFBC decoder is required for this buffer */
 	if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-	     meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) &&
+	     meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	     meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) &&
 	    fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
 		priv->viu.osd1_afbcd = true;
 	else
@@ -181,7 +182,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
 	priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
 
 	if (priv->viu.osd1_afbcd) {
-		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+		    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 			/* This is the internal decoding memory address */
 			priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR;
 			priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE;
@@ -205,7 +207,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
 		priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
 
 	if (priv->viu.osd1_afbcd &&
-	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	    (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	     meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))) {
 		priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN |
 			priv->afbcd.ops->fmt_to_blk_mode(fb->modifier,
 							  fb->format->format);
@@ -357,7 +360,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
 	priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
 	priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
 		priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
 		priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
@@ -377,7 +381,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
 		priv->afbcd.format = fb->format->format;
 
 		/* Calculate decoder write stride */
-		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+		    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 			priv->viu.osd1_blk2_cfg4 =
 				meson_g12a_afbcd_line_stride(priv);
 	}
@@ -408,7 +413,8 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
 	}
 
 	/* Disable OSD1 */
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
 				    priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
 	else
@@ -439,7 +445,8 @@ static bool meson_plane_format_mod_supported(struct drm_plane *plane,
 		return true;
 
 	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) &&
-	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) &&
+	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		return false;
 
 	if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
@@ -546,7 +553,8 @@ int meson_plane_create(struct meson_drm *priv)
 
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
 		format_modifiers = format_modifiers_afbc_gxm;
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		format_modifiers = format_modifiers_afbc_g12a;
 
 	ret = drm_universal_plane_init(priv->drm, plane, 0xFF,
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 3d73d00a1f4c64cb90d2ab78f74133311d028197..c62ee8bac272be035e92dbc8e743b2d4f864bc55 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -328,6 +328,22 @@
 #define VIU_VD2_FMT_CTRL 0x1a88
 #define VIU_VD2_FMT_W 0x1a89
 
+#define VD1_IF0_RANGE_MAP_Y_S4 0x4816
+#define VD1_IF0_RANGE_MAP_CB_S4 0x4817
+#define VD1_IF0_RANGE_MAP_CR_S4 0x4818
+#define VD1_IF0_GEN_REG2_S4 0x4819
+#define VD1_IF0_GEN_REG3_S4 0x481c
+#define VIU_VD1_FMT_CTRL_S4 0x481d
+#define VIU_VD1_FMT_W_S4 0x481e
+
+#define VD2_IF0_RANGE_MAP_Y_S4 0x4896
+#define VD2_IF0_RANGE_MAP_CB_S4 0x4897
+#define VD2_IF0_RANGE_MAP_CR_S4  0x4898
+#define VD2_IF0_GEN_REG2_S4 0x4899
+#define VD2_IF0_GEN_REG3_S4 0x489c
+#define VIU_VD2_FMT_CTRL_S4 0x489d
+#define VIU_VD2_FMT_W_S4    0x489e
+
 /* VIU Matrix Registers */
 #define VIU_OSD1_MATRIX_CTRL 0x1a90
 #define VIU_OSD1_MATRIX_COEF00_01 0x1a91

-- 
2.43.0

[PATCH 05/11] drm: meson: update VIU and VPP support for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Update VIU and VPP initialization for S4 compatibility.
VPP_MISC register definition was different with G12 SoCs,
so disabled watermark control for S4.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_registers.h |  1 +
 drivers/gpu/drm/meson/meson_viu.c       |  9 ++++++---
 drivers/gpu/drm/meson/meson_vpp.c       | 12 +++++++++---
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index c62ee8bac272be035e92dbc8e743b2d4f864bc55..4017c3344b3f90686d1041eda4ff00a549ba6e54 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -463,6 +463,7 @@
 #define		VPP_OSD2_ALPHA_PREMULT          BIT(8)
 #define		VPP_OSD1_ALPHA_PREMULT          BIT(9)
 #define		VPP_VD1_POSTBLEND               BIT(10)
+#define		VPP_WATER_MARK_10BIT            BIT(10)
 #define		VPP_VD2_POSTBLEND               BIT(11)
 #define		VPP_OSD1_POSTBLEND              BIT(12)
 #define		VPP_OSD2_POSTBLEND              BIT(13)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index cd399b0b7181499218a8f969c0d320be88fd93c4..cb3646ccae68f3ce35b1148e5b5df98b0116da96 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -425,7 +425,8 @@ void meson_viu_init(struct meson_drm *priv)
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 		meson_viu_load_matrix(priv);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
 					       true);
 		/* fix green/pink color distortion from vendor u-boot */
@@ -440,7 +441,8 @@ void meson_viu_init(struct meson_drm *priv)
 		VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
 		VIU_OSD_FIFO_LIMITS(2);      /* fifo_lim: 2*16=32 */
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
 	else
 		reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
@@ -467,7 +469,8 @@ void meson_viu_init(struct meson_drm *priv)
 	writel_relaxed(0x00FF00C0,
 			priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		u32 val = (u32)VIU_OSD_BLEND_REORDER(0, 1) |
 			  (u32)VIU_OSD_BLEND_REORDER(1, 0) |
 			  (u32)VIU_OSD_BLEND_REORDER(2, 0) |
diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
index 5df1957c8e41f4e438545f91dd9eecb423e53b91..92e7d26abaa8771e5cc99a03e5a5ff32f5a48d30 100644
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -102,11 +102,13 @@ void meson_vpp_init(struct meson_drm *priv)
 				priv->io_base + _REG(VPP_DUMMY_DATA1));
 		writel_relaxed(0x42020,
 				priv->io_base + _REG(VPP_DUMMY_DATA));
-	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
 
 	/* Initialize vpu fifo control registers */
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
 			       priv->io_base + _REG(VPP_OFIFO_SIZE));
 	else
@@ -115,7 +117,8 @@ void meson_vpp_init(struct meson_drm *priv)
 	writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
 		       priv->io_base + _REG(VPP_HOLD_LINES));
 
-	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) &&
+	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		/* Turn off preblend */
 		writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
 				    priv->io_base + _REG(VPP_MISC));
@@ -137,6 +140,9 @@ void meson_vpp_init(struct meson_drm *priv)
 				priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
 	}
 
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		writel_bits_relaxed(VPP_WATER_MARK_10BIT, 0, priv->io_base + _REG(VPP_MISC));
+
 	/* Disable Scalers */
 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));

-- 
2.43.0

[PATCH 06/11] drm: meson: add meson_dw_hdmi support for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add S4 dw_hdmi register access method.
Adjust clock, power domain, and PHY configurations
to support HDMI on the S4.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_dw_hdmi.c | 244 ++++++++++++++++++++++++++++------
 drivers/gpu/drm/meson/meson_dw_hdmi.h | 126 ++++++++++++++++++
 2 files changed, 329 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 0d7c68b29dfff43ef276734368b15da9ee497919..bf59e68bba498620dd6e503de4e5e087637c17a0 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include <linux/reset.h>
+#include <linux/arm-smccc.h>
 
 #include <drm/bridge/dw_hdmi.h>
 #include <drm/drm_atomic_helper.h>
@@ -90,29 +91,6 @@
  * - CEC Management
  */
 
-/* TOP Block Communication Channel */
-#define HDMITX_TOP_ADDR_REG	0x0
-#define HDMITX_TOP_DATA_REG	0x4
-#define HDMITX_TOP_CTRL_REG	0x8
-#define HDMITX_TOP_G12A_OFFSET	0x8000
-
-/* Controller Communication Channel */
-#define HDMITX_DWC_ADDR_REG	0x10
-#define HDMITX_DWC_DATA_REG	0x14
-#define HDMITX_DWC_CTRL_REG	0x18
-
-/* HHI Registers */
-#define HHI_MEM_PD_REG0		0x100 /* 0x40 */
-#define HHI_HDMI_CLK_CNTL	0x1cc /* 0x73 */
-#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 */
-#define HHI_HDMI_PHY_CNTL1	0x3a4 /* 0xe9 */
-#define  PHY_CNTL1_INIT		0x03900000
-#define  PHY_INVERT		BIT(17)
-#define HHI_HDMI_PHY_CNTL2	0x3a8 /* 0xea */
-#define HHI_HDMI_PHY_CNTL3	0x3ac /* 0xeb */
-#define HHI_HDMI_PHY_CNTL4	0x3b0 /* 0xec */
-#define HHI_HDMI_PHY_CNTL5	0x3b4 /* 0xed */
-
 static DEFINE_SPINLOCK(reg_lock);
 
 enum meson_venc_source {
@@ -185,6 +163,39 @@ static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi,
 	return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
 }
 
+static unsigned int dw_hdmi_s4_top_read(struct meson_dw_hdmi *dw_hdmi,
+					  unsigned int addr)
+{
+	struct arm_smccc_res res;
+	unsigned int val;
+
+	switch (addr) {
+	case HDMITX_TOP_SKP_CNTL_STAT:
+	case HDMITX_TOP_NONCE_0:
+	case HDMITX_TOP_NONCE_1:
+	case HDMITX_TOP_NONCE_2:
+	case HDMITX_TOP_NONCE_3:
+	case HDMITX_TOP_PKF_0:
+	case HDMITX_TOP_PKF_1:
+	case HDMITX_TOP_PKF_2:
+	case HDMITX_TOP_PKF_3:
+	case HDMITX_TOP_DUK_0:
+	case HDMITX_TOP_DUK_1:
+	case HDMITX_TOP_DUK_2:
+	case HDMITX_TOP_DUK_3:
+	case HDMITX_TOP_HDCP22_BSOD:
+		addr |= TOP_SEC_OFFSET_MASK;
+		arm_smccc_smc(HDMI_SEC_READ_REG, (unsigned long)addr, 0, 0, 0, 0, 0, 0, &res);
+		val = (unsigned int)((res.a0) & 0xffffffff);
+		break;
+	default:
+		val = readl(dw_hdmi->hdmitx + HDMITX_TOP_S4_OFFSET + (addr << 2));
+		break;
+	}
+
+	return val;
+}
+
 static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
 				     unsigned int addr, unsigned int data)
 {
@@ -208,6 +219,35 @@ static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi,
 	writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
 }
 
+static inline void dw_hdmi_s4_top_write(struct meson_dw_hdmi *dw_hdmi,
+					  unsigned int addr, unsigned int data)
+{
+	struct arm_smccc_res res;
+
+	switch (addr) {
+	case HDMITX_TOP_SKP_CNTL_STAT:
+	case HDMITX_TOP_NONCE_0:
+	case HDMITX_TOP_NONCE_1:
+	case HDMITX_TOP_NONCE_2:
+	case HDMITX_TOP_NONCE_3:
+	case HDMITX_TOP_PKF_0:
+	case HDMITX_TOP_PKF_1:
+	case HDMITX_TOP_PKF_2:
+	case HDMITX_TOP_PKF_3:
+	case HDMITX_TOP_DUK_0:
+	case HDMITX_TOP_DUK_1:
+	case HDMITX_TOP_DUK_2:
+	case HDMITX_TOP_DUK_3:
+	case HDMITX_TOP_HDCP22_BSOD:
+		addr |= TOP_SEC_OFFSET_MASK;
+		arm_smccc_smc(HDMI_SEC_WRITE_REG, (unsigned long)addr, data, 0, 0, 0, 0, 0, &res);
+		break;
+	default:
+		writel(data, dw_hdmi->hdmitx + HDMITX_TOP_S4_OFFSET + (addr << 2));
+		break;
+	}
+}
+
 /* Helper to change specific bits in PHY registers */
 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
 					  unsigned int addr,
@@ -249,6 +289,38 @@ static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi,
 	return readb(dw_hdmi->hdmitx + addr);
 }
 
+static unsigned int dw_hdmi_s4_dwc_read(struct meson_dw_hdmi *dw_hdmi,
+					  unsigned int addr)
+{
+	struct arm_smccc_res res;
+	unsigned int val;
+
+	switch (addr) {
+	case HDMITX_DWC_MC_CLKDIS:
+	case HDMITX_DWC_A_HDCPCFG0:
+	case HDMITX_DWC_A_HDCPCFG1:
+	case HDMITX_DWC_HDCPREG_SEED0:
+	case HDMITX_DWC_HDCPREG_SEED1:
+	case HDMITX_DWC_HDCPREG_DPK0:
+	case HDMITX_DWC_HDCPREG_DPK1:
+	case HDMITX_DWC_HDCPREG_DPK2:
+	case HDMITX_DWC_HDCPREG_DPK3:
+	case HDMITX_DWC_HDCPREG_DPK4:
+	case HDMITX_DWC_HDCPREG_DPK5:
+	case HDMITX_DWC_HDCPREG_DPK6:
+	case HDMITX_DWC_HDCP22REG_CTRL:
+		addr |= DWC_SEC_OFFSET_MASK;
+		arm_smccc_smc(HDMI_SEC_READ_REG, (unsigned long)addr, 0, 0, 0, 0, 0, 0, &res);
+		val = (unsigned int)((res.a0) & 0xffffffff);
+		break;
+	default:
+		val = readb(dw_hdmi->hdmitx + addr);
+		break;
+	}
+
+	return val;
+}
+
 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
 				     unsigned int addr, unsigned int data)
 {
@@ -272,6 +344,34 @@ static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi,
 	writeb(data, dw_hdmi->hdmitx + addr);
 }
 
+static inline void dw_hdmi_s4_dwc_write(struct meson_dw_hdmi *dw_hdmi,
+					  unsigned int addr, unsigned int data)
+{
+	struct arm_smccc_res res;
+
+	switch (addr) {
+	case HDMITX_DWC_MC_CLKDIS:
+	case HDMITX_DWC_A_HDCPCFG0:
+	case HDMITX_DWC_A_HDCPCFG1:
+	case HDMITX_DWC_HDCPREG_SEED0:
+	case HDMITX_DWC_HDCPREG_SEED1:
+	case HDMITX_DWC_HDCPREG_DPK0:
+	case HDMITX_DWC_HDCPREG_DPK1:
+	case HDMITX_DWC_HDCPREG_DPK2:
+	case HDMITX_DWC_HDCPREG_DPK3:
+	case HDMITX_DWC_HDCPREG_DPK4:
+	case HDMITX_DWC_HDCPREG_DPK5:
+	case HDMITX_DWC_HDCPREG_DPK6:
+	case HDMITX_DWC_HDCP22REG_CTRL:
+		addr |= DWC_SEC_OFFSET_MASK;
+		arm_smccc_smc(HDMI_SEC_WRITE_REG, (unsigned long)addr, data, 0, 0, 0, 0, 0, &res);
+		break;
+	default:
+		writeb(data, dw_hdmi->hdmitx + addr);
+		break;
+	}
+}
+
 /* Bridge */
 
 /* Setup PHY bandwidth modes */
@@ -337,6 +437,23 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
 			regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
 			regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
 		}
+	} else if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) {
+		if (pixel_clock >= 371250) {
+			/* 5.94Gbps, 4.5Gbps, 3.7125Gbps */
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+		} else if (pixel_clock >= 297000) {
+			/* 2.97Gbps */
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+		} else {
+			/* 1.485Gbps, and below */
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
+			regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+		}
 	}
 }
 
@@ -344,13 +461,23 @@ static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
 {
 	struct meson_drm *priv = dw_hdmi->priv;
 
-	/* Enable and software reset */
-	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
+	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) {
+		/* Enable and software reset */
+		regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0xf);
 
-	mdelay(2);
+		mdelay(2);
 
-	/* Enable and unreset */
-	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
+		/* Enable and unreset */
+		regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0xe);
+	} else {
+		/* Enable and software reset */
+		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
+
+		mdelay(2);
+
+		/* Enable and unreset */
+		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
+	}
 
 	mdelay(2);
 }
@@ -396,7 +523,10 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
 	meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
 
 	/* Disable clock, fifo, fifo_wr */
-	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
+	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi"))
+		regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0);
+	else
+		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
 
 	dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
 
@@ -449,8 +579,15 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
 	DRM_DEBUG_DRIVER("\n");
 
 	/* Fallback to init mode */
-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
+	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) {
+		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL1,
+			     dw_hdmi->data->cntl1_init);
+		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0,
+			     dw_hdmi->data->cntl0_init);
+	} else {
+		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
+		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
+	}
 }
 
 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
@@ -595,23 +732,36 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
 	.cntl1_init = PHY_CNTL1_INIT,
 };
 
+static const struct meson_dw_hdmi_data meson_dw_hdmi_s4_data = {
+	.top_read = dw_hdmi_s4_top_read,
+	.top_write = dw_hdmi_s4_top_write,
+	.dwc_read = dw_hdmi_s4_dwc_read,
+	.dwc_write = dw_hdmi_s4_dwc_write,
+	.cntl0_init = 0x0,
+	.cntl1_init = PHY_CNTL1_INIT,
+};
+
 static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
 {
 	struct meson_drm *priv = meson_dw_hdmi->priv;
 
-	/* Enable clocks */
-	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
-
-	/* Bring HDMITX MEM output of power down */
-	regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
-
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_update_bits(priv->hhi, CLKCTRL_HDMI_CLK_CTRL, 0xffff, 0x100);
+		regmap_update_bits(priv->pwrctrl, PWRCTRL_MEM_PD11, 0xff << 8, 0);
+	} else {
+		/* Enable clocks */
+		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
+		/* Bring HDMITX MEM output of power down */
+		regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
+	}
 	/* Reset HDMITX APB & TX & PHY */
 	reset_control_reset(meson_dw_hdmi->hdmitx_apb);
 	reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);
 	reset_control_reset(meson_dw_hdmi->hdmitx_phy);
 
 	/* Enable APB3 fail on error */
-	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
+	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) &&
+	    !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
 		writel_bits_relaxed(BIT(15), BIT(15),
 				    meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
 		writel_bits_relaxed(BIT(15), BIT(15),
@@ -631,8 +781,15 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
 
 	/* Setup PHY */
-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
+	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi")) {
+		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL1,
+			     meson_dw_hdmi->data->cntl1_init);
+		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0,
+			     meson_dw_hdmi->data->cntl0_init);
+	} else {
+		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
+		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
+	}
 
 	/* Enable HDMI-TX Interrupt */
 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
@@ -766,10 +923,13 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
 	dw_plat_data->ycbcr_420_allowed = true;
 	dw_plat_data->disable_cec = true;
 	dw_plat_data->output_port = 1;
+	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi"))
+		dw_plat_data->phy_force_vendor = 1;
 
 	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
 	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
-	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
+	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi") ||
+	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi"))
 		dw_plat_data->use_drm_infoframe = true;
 
 	platform_set_drvdata(pdev, meson_dw_hdmi);
@@ -850,6 +1010,8 @@ static const struct of_device_id meson_dw_hdmi_of_table[] = {
 	  .data = &meson_dw_hdmi_gxl_data },
 	{ .compatible = "amlogic,meson-g12a-dw-hdmi",
 	  .data = &meson_dw_hdmi_g12a_data },
+	{ .compatible = "amlogic,meson-s4-dw-hdmi",
+	  .data = &meson_dw_hdmi_s4_data },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table);
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.h b/drivers/gpu/drm/meson/meson_dw_hdmi.h
index 08e1c14e4ea07c694f2c5fccbbf593661a8a3feb..66203b59e5e0ca67463ec5c79165e757f3a24406 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.h
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.h
@@ -8,6 +8,16 @@
 #ifndef __MESON_DW_HDMI_H
 #define __MESON_DW_HDMI_H
 
+/* TOP-level wrapper registers addresses
+ * bit24: 1 means secure access
+ * bit28: 1 means DWC, 0 means TOP
+ */
+#define TOP_SEC_OFFSET_MASK                     BIT(24)
+#define DWC_SEC_OFFSET_MASK                     (BIT(24) | BIT(28))
+
+#define HDMI_SEC_READ_REG                       (0x82000018)
+#define HDMI_SEC_WRITE_REG                      (0x82000019)
+
 /*
  * Bit 15-10: RW Reserved. Default 1 starting from G12A
  * Bit 9 RW sw_reset_i2c starting from G12A
@@ -157,4 +167,120 @@
  */
 #define HDMITX_TOP_STAT0                        (0x00E)
 
+#define HDMITX_TOP_SKP_CNTL_STAT                (0x010)
+#define HDMITX_TOP_NONCE_0                      (0x011)
+#define HDMITX_TOP_NONCE_1                      (0x012)
+#define HDMITX_TOP_NONCE_2                      (0x013)
+#define HDMITX_TOP_NONCE_3                      (0x014)
+#define HDMITX_TOP_PKF_0                        (0x015)
+#define HDMITX_TOP_PKF_1                        (0x016)
+#define HDMITX_TOP_PKF_2                        (0x017)
+#define HDMITX_TOP_PKF_3                        (0x018)
+#define HDMITX_TOP_DUK_0                        (0x019)
+#define HDMITX_TOP_DUK_1                        (0x01A)
+#define HDMITX_TOP_DUK_2                        (0x01B)
+#define HDMITX_TOP_DUK_3                        (0x01C)
+
+/* [26:24] infilter_ddc_intern_clk_divide */
+/* [23:16] infilter_ddc_sample_clk_divide */
+/* [10: 8] infilter_cec_intern_clk_divide */
+/* [ 7: 0] infilter_cec_sample_clk_divide */
+#define HDMITX_TOP_INFILTER                     (0x01D)
+#define HDMITX_TOP_NSEC_SCRATCH                 (0x01E)
+#define HDMITX_TOP_SEC_SCRATCH                  (0x01F)
+#define HDMITX_TOP_EMP_CNTL0                    (0x020)
+#define HDMITX_TOP_EMP_CNTL1                    (0x021)
+#define HDMITX_TOP_EMP_MEMADDR_START            (0x022)
+#define HDMITX_TOP_EMP_STAT0                    (0x023)
+#define HDMITX_TOP_EMP_STAT1                    (0x024)
+#define HDMITX_TOP_AXI_ASYNC_CNTL0              (0x025)
+#define HDMITX_TOP_AXI_ASYNC_CNTL1              (0x026)
+#define HDMITX_TOP_AXI_ASYNC_STAT0              (0x027)
+#define HDMITX_TOP_I2C_BUSY_CNT_MAX             (0x028)
+#define HDMITX_TOP_I2C_BUSY_CNT_STAT            (0x029)
+#define HDMITX_TOP_HDCP22_BSOD                  (0x02A)
+#define HDMITX_TOP_DDC_CNTL                     (0x02B)
+#define HDMITX_TOP_DISABLE_NULL                 (0x030)
+#define HDMITX_TOP_HDCP14_UNENCRYPT             (0x031)
+#define HDMITX_TOP_MISC_CNTL                    (0x032)
+#define HDMITX_TOP_HDCP22_MIN_SIZE              (0x035)
+
+#define HDMITX_TOP_DONT_TOUCH0                  (0x0FE)
+#define HDMITX_TOP_DONT_TOUCH1                  (0x0FF)
+
+/* DWC_HDMI_TX Controller SEC registers addresses */
+/* Main Controller Registers */
+/* [  6] hdcpclk_disable */
+/* [  5] cecclk_disable */
+/* [  4] cscclk_disable */
+/* [  3] audclk_disable */
+/* [  2] prepclk_disable */
+/* [  1] tmdsclk_disable */
+/* [  0] pixelclk_disable */
+#define HDMITX_DWC_MC_CLKDIS                    (0x4001)
+
+/* HDCP Encryption Engine Registers */
+#define HDMITX_DWC_A_HDCPCFG0                   (0x5000)
+
+/* [  4] hdcp_lock */
+/* [  3] dissha1check */
+/* [  2] ph2upshiftenc */
+/* [  1] encryptiondisable */
+/* [  0] swresetn. Write 0 to activate, self-clear to 1. */
+#define HDMITX_DWC_A_HDCPCFG1                   (0x5001)
+
+/* Encrypted DPK Embedded Storage Registers */
+#define HDMITX_DWC_HDCPREG_SEED0                (0x7810)
+#define HDMITX_DWC_HDCPREG_SEED1                (0x7811)
+#define HDMITX_DWC_HDCPREG_DPK0                 (0x7812)
+#define HDMITX_DWC_HDCPREG_DPK1                 (0x7813)
+#define HDMITX_DWC_HDCPREG_DPK2                 (0x7814)
+#define HDMITX_DWC_HDCPREG_DPK3                 (0x7815)
+#define HDMITX_DWC_HDCPREG_DPK4                 (0x7816)
+#define HDMITX_DWC_HDCPREG_DPK5                 (0x7817)
+#define HDMITX_DWC_HDCPREG_DPK6                 (0x7818)
+
+/* HDCP22 Registers */
+#define HDMITX_DWC_HDCP22REG_CTRL               (0x7904)
+
+/* TOP Block Communication Channel */
+#define HDMITX_TOP_ADDR_REG                     0x0
+#define HDMITX_TOP_DATA_REG                     0x4
+#define HDMITX_TOP_CTRL_REG                     0x8
+#define HDMITX_TOP_G12A_OFFSET                  0x8000
+#define HDMITX_TOP_S4_OFFSET                    0x8000
+
+/* Controller Communication Channel */
+#define HDMITX_DWC_ADDR_REG                     0x10
+#define HDMITX_DWC_DATA_REG                     0x14
+#define HDMITX_DWC_CTRL_REG                     0x18
+
+/* HHI Registers */
+#define HHI_MEM_PD_REG0                         0x100 /* 0x40 */
+#define HHI_HDMI_CLK_CNTL                       0x1cc /* 0x73 */
+#define HHI_HDMI_PHY_CNTL0                      0x3a0 /* 0xe8 */
+#define HHI_HDMI_PHY_CNTL1                      0x3a4 /* 0xe9 */
+#define HHI_HDMI_PHY_CNTL2                      0x3a8 /* 0xea */
+#define HHI_HDMI_PHY_CNTL3                      0x3ac /* 0xeb */
+#define HHI_HDMI_PHY_CNTL4                      0x3b0 /* 0xec */
+#define HHI_HDMI_PHY_CNTL5                      0x3b4 /* 0xed */
+
+/*ANA Registers */
+/* REG_BASE:  REGISTER_BASE_ADDR = 0xfe00c000 */
+#define PWRCTRL_MEM_PD11                        0x06c  /* 0x1b */
+
+/* REG_BASE:  REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_HDMI_CLK_CTRL                   0x0e0  /* 0x38 */
+
+/* REG_BASE:  REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPHY_CTRL0                   0x200  /* 0x80 */
+#define ANACTRL_HDMIPHY_CTRL1                   0x204  /* 0x81 */
+#define PHY_CNTL1_INIT                          0x03900000
+#define PHY_INVERT                              BIT(17)
+#define ANACTRL_HDMIPHY_CTRL2                   0x208  /* 0x82 */
+#define ANACTRL_HDMIPHY_CTRL3                   0x20c  /* 0x83 */
+#define ANACTRL_HDMIPHY_CTRL4                   0x210  /* 0x84 */
+#define ANACTRL_HDMIPHY_CTRL5                   0x214  /* 0x85 */
+#define ANACTRL_HDMIPHY_STS                     0x218  /* 0x86 */
+
 #endif /* __MESON_DW_HDMI_H */

-- 
2.43.0

Re: [PATCH 06/11] drm: meson: add meson_dw_hdmi support for S4

[Krzysztof Kozlowski]

On 10/01/2025 06:39, Ao Xu via B4 Relay wrote:
>  	/* Setup PHY */
> -	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
> -	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
> +	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi")) {
> +		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL1,
> +			     meson_dw_hdmi->data->cntl1_init);
> +		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0,
> +			     meson_dw_hdmi->data->cntl0_init);
> +	} else {
> +		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
> +		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
> +	}
>  
>  	/* Enable HDMI-TX Interrupt */
>  	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
> @@ -766,10 +923,13 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
>  	dw_plat_data->ycbcr_420_allowed = true;
>  	dw_plat_data->disable_cec = true;
>  	dw_plat_data->output_port = 1;
> +	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi"))
> +		dw_plat_data->phy_force_vendor = 1;
>  
>  	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
>  	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
> -	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
> +	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi") ||
> +	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi"))
>  		dw_plat_data->use_drm_infoframe = true;
>  
You should properly define driver/match data, instead of running
compatibility check 10 times in your driver.

This is unscalable and unmaintainable approach.

Best regards,
Krzysztof

[PATCH 07/11] drm: meson: change api call parameter

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Adjust the parameters passed to specific API calls in the
Meson HDMI encoder to align with hardware requirements.
Configure VCLK to use double pixels for
480p and 576p resolutions in the Amlogic S4.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_encoder_hdmi.c | 19 +++++++++++++++----
 drivers/gpu/drm/meson/meson_venc.c         | 12 ++++++------
 drivers/gpu/drm/meson/meson_venc.h         |  4 ++--
 3 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
index 0593a1cde906ffab10c010c40942fb910059b2ab..5fde4cfc79ad66d3bb6c15cedce536f1346fce34 100644
--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
@@ -98,7 +98,7 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi,
 	hdmi_freq = vclk_freq;
 
 	/* VENC double pixels for 1080i, 720p and YUV420 modes */
-	if (meson_venc_hdmi_venc_repeat(vic) ||
+	if (meson_venc_hdmi_venc_repeat(priv, vic) ||
 	    encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24)
 		venc_freq *= 2;
 
@@ -107,6 +107,11 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi,
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		venc_freq /= 2;
 
+	/* VCLK double pixels for 480p and 576p on S4 */
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		if (vic == 2 || vic == 3 || vic == 17 || vic == 18)
+			vclk_freq *= 2;
+
 	dev_dbg(priv->dev, "vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n",
 		phy_freq, vclk_freq, venc_freq, hdmi_freq,
 		priv->venc.hdmi_use_enci);
@@ -146,7 +151,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri
 
 		return meson_vclk_dmt_supported_freq(priv, mode->clock);
 	/* Check against supported VIC modes */
-	} else if (!meson_venc_hdmi_supported_vic(vic))
+	} else if (!meson_venc_hdmi_supported_vic(priv, vic))
 		return MODE_BAD;
 
 	vclk_freq = mode->clock;
@@ -168,7 +173,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri
 	hdmi_freq = vclk_freq;
 
 	/* VENC double pixels for 1080i, 720p and YUV420 modes */
-	if (meson_venc_hdmi_venc_repeat(vic) ||
+	if (meson_venc_hdmi_venc_repeat(priv, vic) ||
 	    drm_mode_is_420_only(display_info, mode) ||
 	    (!is_hdmi2_sink &&
 	     drm_mode_is_420_also(display_info, mode)))
@@ -179,6 +184,11 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		venc_freq /= 2;
 
+	/* VCLK double pixels for 480p and 576p on S4 */
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		if (vic == 2 || vic == 3 || vic == 17 || vic == 18)
+			vclk_freq *= 2;
+
 	dev_dbg(priv->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n",
 		__func__, phy_freq, vclk_freq, venc_freq, hdmi_freq);
 
@@ -444,7 +454,8 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv)
 
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
 	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) ||
+	    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
 		drm_connector_attach_hdr_output_metadata_property(meson_encoder_hdmi->connector);
 
 	drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8);
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 3bf0d6e4fc30ae1e06f6ba77157325af416c786f..5c461b27ae49317d8f430dc55606c8e11a536240 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -878,7 +878,7 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
 }
 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
 
-bool meson_venc_hdmi_supported_vic(int vic)
+bool meson_venc_hdmi_supported_vic(struct meson_drm *priv, int vic)
 {
 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 
@@ -917,7 +917,7 @@ static void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode,
 	dmt_mode->encp.max_lncnt = mode->vtotal - 1;
 }
 
-static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
+static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(struct meson_drm *priv, int vic)
 {
 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 
@@ -930,7 +930,7 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
 	return NULL;
 }
 
-bool meson_venc_hdmi_venc_repeat(int vic)
+bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic)
 {
 	/* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
 	if (vic == 6 || vic == 7 || /* 480i */
@@ -989,8 +989,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
 		venc_hdmi_latency = 1;
 	}
 
-	if (meson_venc_hdmi_supported_vic(vic)) {
-		vmode = meson_venc_hdmi_get_vic_vmode(vic);
+	if (meson_venc_hdmi_supported_vic(priv, vic)) {
+		vmode = meson_venc_hdmi_get_vic_vmode(priv, vic);
 		if (!vmode) {
 			dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
 				DRM_MODE_FMT "\n", __func__,
@@ -1004,7 +1004,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
 	}
 
 	/* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
-	if (meson_venc_hdmi_venc_repeat(vic))
+	if (meson_venc_hdmi_venc_repeat(priv, vic))
 		venc_repeat = true;
 
 	eof_lines = mode->vsync_start - mode->vdisplay;
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
index 0f59adb1c6db08ca39d0c556875cf5d0d8df430a..7cc6841f633048364c9880f5d1f0e18e3056c9f8 100644
--- a/drivers/gpu/drm/meson/meson_venc.h
+++ b/drivers/gpu/drm/meson/meson_venc.h
@@ -54,8 +54,8 @@ void meson_encl_load_gamma(struct meson_drm *priv);
 /* HDMI Clock parameters */
 enum drm_mode_status
 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
-bool meson_venc_hdmi_supported_vic(int vic);
-bool meson_venc_hdmi_venc_repeat(int vic);
+bool meson_venc_hdmi_supported_vic(struct meson_drm *priv, int vic);
+bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic);
 
 /* CVBS Timings and Parameters */
 extern struct meson_cvbs_enci_mode meson_cvbs_enci_pal;

-- 
2.43.0

[PATCH 08/11] drm: meson: add hdmitx vmode timing support for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Introduce support for HDMI TX video mode (vmode) timing in the
Meson VENC driver for the Amlogic S4 SoC. These updates enable
reliable HDMI output with correct timing for S4 devices.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_venc.c | 334 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 328 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 5c461b27ae49317d8f430dc55606c8e11a536240..58e8e3bc854070ba152ee6dd4abde38ee1e28266 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -68,6 +68,12 @@
 #define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */
 #define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
 
+/* ANA Registers */
+#define CLKCTRL_SYS_CLK_EN0_REG2	0x04c /* 0x13 offset in data sheet */
+#define ANACTRL_HDMIPHY_CTRL0		0x200 /* 0x80 */
+#define ANACTRL_VDAC_CTRL0		0x2c0 /* 0xb0 offset in data sheet */
+#define ANACTRL_VDAC_CTRL1		0x2c4 /* 0xb1 offset in data sheet */
+
 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
 	.mode_tag = MESON_VENC_MODE_CVBS_PAL,
 	.hso_begin = 3,
@@ -228,6 +234,52 @@ static union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_480p = {
+	.encp = {
+		.dvi_settings = 0x21,
+		.video_mode = 0x4000,
+		.video_mode_adv = 0x8,
+		.video_prog_mode = 0,
+		.video_prog_mode_present = true,
+		.video_sync_mode = 7,
+		.video_sync_mode_present = true,
+		/* video_yc_dly */
+		/* video_rgb_ctrl */
+		.video_filt_ctrl = 0x2052,
+		.video_filt_ctrl_present = true,
+		/* video_ofld_voav_ofst */
+		.yfp1_htime = 244,
+		.yfp2_htime = 1630,
+		.max_pxcnt = 857,
+		.hspuls_begin = 0x22,
+		.hspuls_end = 0xa0,
+		.hspuls_switch = 88,
+		.vspuls_begin = 0,
+		.vspuls_end = 1589,
+		.vspuls_bline = 0,
+		.vspuls_eline = 5,
+		.havon_begin = 122,
+		.havon_end = 841,
+		.vavon_bline = 36,
+		.vavon_eline = 515,
+		/* eqpuls_begin */
+		/* eqpuls_end */
+		/* eqpuls_bline */
+		/* eqpuls_eline */
+		.hso_begin = 0,
+		.hso_end = 62,
+		.vso_begin = 30,
+		.vso_end = 50,
+		.vso_bline = 0,
+		/* vso_eline */
+		.sy_val = 8,
+		.sy_val_present = true,
+		.sy2_val = 0x1d8,
+		.sy2_val_present = true,
+		.max_lncnt = 524,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
 	.encp = {
 		.dvi_settings = 0x21,
@@ -320,6 +372,52 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_576p = {
+	.encp = {
+		.dvi_settings = 0x21,
+		.video_mode = 0x4000,
+		.video_mode_adv = 0x8,
+		.video_prog_mode = 0,
+		.video_prog_mode_present = true,
+		.video_sync_mode = 7,
+		.video_sync_mode_present = true,
+		/* video_yc_dly */
+		/* video_rgb_ctrl */
+		.video_filt_ctrl = 0x52,
+		.video_filt_ctrl_present = true,
+		/* video_ofld_voav_ofst */
+		.yfp1_htime = 235,
+		.yfp2_htime = 1674,
+		.max_pxcnt = 863,
+		.hspuls_begin = 0,
+		.hspuls_end = 0x80,
+		.hspuls_switch = 88,
+		.vspuls_begin = 0,
+		.vspuls_end = 1599,
+		.vspuls_bline = 0,
+		.vspuls_eline = 4,
+		.havon_begin = 132,
+		.havon_end = 851,
+		.vavon_bline = 44,
+		.vavon_eline = 619,
+		/* eqpuls_begin */
+		/* eqpuls_end */
+		/* eqpuls_bline */
+		/* eqpuls_eline */
+		.hso_begin = 0,
+		.hso_end = 64,
+		.vso_begin = 30,
+		.vso_end = 50,
+		.vso_bline = 5,
+		/* vso_eline */
+		.sy_val = 8,
+		.sy_val_present = true,
+		.sy2_val = 0x1d8,
+		.sy2_val_present = true,
+		.max_lncnt = 624,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
 	.encp = {
 		.dvi_settings = 0x2029,
@@ -362,6 +460,48 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_720p60 = {
+	.encp = {
+		.dvi_settings = 0x2029,
+		.video_mode = 0x4040,
+		.video_mode_adv = 0x18,
+		/* video_prog_mode */
+		/* video_sync_mode */
+		/* video_yc_dly */
+		/* video_rgb_ctrl */
+		/* video_filt_ctrl */
+		/* video_ofld_voav_ofst */
+		.yfp1_htime = 648,
+		.yfp2_htime = 3207,
+		.max_pxcnt = 1649,
+		.hspuls_begin = 80,
+		.hspuls_end = 240,
+		.hspuls_switch = 80,
+		.vspuls_begin = 688,
+		.vspuls_end = 3248,
+		.vspuls_bline = 4,
+		.vspuls_eline = 8,
+		.havon_begin = 260,
+		.havon_end = 1539,
+		.vavon_bline = 29,
+		.vavon_eline = 749,
+		/* eqpuls_begin */
+		/* eqpuls_end */
+		/* eqpuls_bline */
+		/* eqpuls_eline */
+		.hso_begin = 0,
+		.hso_end = 168,
+		.vso_begin = 168,
+		.vso_end = 256,
+		.vso_bline = 0,
+		.vso_eline = 5,
+		.vso_eline_present = true,
+		/* sy_val */
+		/* sy2_val */
+		.max_lncnt = 749,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
 	.encp = {
 		.dvi_settings = 0x202d,
@@ -407,6 +547,51 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_720p50 = {
+	.encp = {
+		.dvi_settings = 0x202d,
+		.video_mode = 0x4040,
+		.video_mode_adv = 0x18,
+		.video_prog_mode = 0x100,
+		.video_prog_mode_present = true,
+		.video_sync_mode = 0x407,
+		.video_sync_mode_present = true,
+		.video_yc_dly = 0,
+		.video_yc_dly_present = true,
+		/* video_rgb_ctrl */
+		/* video_filt_ctrl */
+		/* video_ofld_voav_ofst */
+		.yfp1_htime = 648,
+		.yfp2_htime = 3207,
+		.max_pxcnt = 1979,
+		.hspuls_begin = 80,
+		.hspuls_end = 240,
+		.hspuls_switch = 80,
+		.vspuls_begin = 688,
+		.vspuls_end = 3248,
+		.vspuls_bline = 4,
+		.vspuls_eline = 8,
+		.havon_begin = 260,
+		.havon_end = 1539,
+		.vavon_bline = 25,
+		.vavon_eline = 744,
+		/* eqpuls_begin */
+		/* eqpuls_end */
+		/* eqpuls_bline */
+		/* eqpuls_eline */
+		.hso_begin = 0,
+		.hso_end = 40,
+		.vso_begin = 30,
+		.vso_end = 50,
+		.vso_bline = 0,
+		.vso_eline = 5,
+		.vso_eline_present = true,
+		/* sy_val */
+		/* sy2_val */
+		.max_lncnt = 749,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
 	.encp = {
 		.dvi_settings = 0x2029,
@@ -456,6 +641,55 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_1080i60 = {
+	.encp = {
+		.dvi_settings = 0x2029,
+		.video_mode = 0x5ffc,
+		.video_mode_adv = 0x18,
+		.video_prog_mode = 0x100,
+		.video_prog_mode_present = true,
+		.video_sync_mode = 0x207,
+		.video_sync_mode_present = true,
+		/* video_yc_dly */
+		/* video_rgb_ctrl */
+		/* video_filt_ctrl */
+		.video_ofld_voav_ofst = 0x11,
+		.video_ofld_voav_ofst_present = true,
+		.yfp1_htime = 516,
+		.yfp2_htime = 4355,
+		.max_pxcnt = 2199,
+		.hspuls_begin = 88,
+		.hspuls_end = 264,
+		.hspuls_switch = 88,
+		.vspuls_begin = 440,
+		.vspuls_end = 2200,
+		.vspuls_bline = 0,
+		.vspuls_eline = 4,
+		.havon_begin = 192,
+		.havon_end = 2111,
+		.vavon_bline = 20,
+		.vavon_eline = 559,
+		.eqpuls_begin = 2288,
+		.eqpuls_begin_present = true,
+		.eqpuls_end = 2464,
+		.eqpuls_end_present = true,
+		.eqpuls_bline = 0,
+		.eqpuls_bline_present = true,
+		.eqpuls_eline = 4,
+		.eqpuls_eline_present = true,
+		.hso_begin = 0,
+		.hso_end = 44,
+		.vso_begin = 30,
+		.vso_end = 50,
+		.vso_bline = 0,
+		.vso_eline = 5,
+		.vso_eline_present = true,
+		/* sy_val */
+		/* sy2_val */
+		.max_lncnt = 1124,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
 	.encp = {
 		.dvi_settings = 0x202d,
@@ -505,6 +739,55 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
 	},
 };
 
+static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_1080i50 = {
+	.encp = {
+		.dvi_settings = 0x202d,
+		.video_mode = 0x5ffc,
+		.video_mode_adv = 0x18,
+		.video_prog_mode = 0x100,
+		.video_prog_mode_present = true,
+		.video_sync_mode = 0x7,
+		.video_sync_mode_present = true,
+		/* video_yc_dly */
+		/* video_rgb_ctrl */
+		/* video_filt_ctrl */
+		.video_ofld_voav_ofst = 0x11,
+		.video_ofld_voav_ofst_present = true,
+		.yfp1_htime = 526,
+		.yfp2_htime = 4365,
+		.max_pxcnt = 2639,
+		.hspuls_begin = 88,
+		.hspuls_end = 264,
+		.hspuls_switch = 88,
+		.vspuls_begin = 440,
+		.vspuls_end = 2200,
+		.vspuls_bline = 0,
+		.vspuls_eline = 4,
+		.havon_begin = 192,
+		.havon_end = 2111,
+		.vavon_bline = 20,
+		.vavon_eline = 559,
+		.eqpuls_begin = 2288,
+		.eqpuls_begin_present = true,
+		.eqpuls_end = 2464,
+		.eqpuls_end_present = true,
+		.eqpuls_bline = 0,
+		.eqpuls_bline_present = true,
+		.eqpuls_eline = 4,
+		.eqpuls_eline_present = true,
+		.hso_begin = 0,
+		.hso_end = 44,
+		.vso_begin = 30,
+		.vso_end = 50,
+		.vso_bline = 0,
+		.vso_eline = 5,
+		.vso_eline_present = true,
+		/* sy_val */
+		/* sy2_val */
+		.max_lncnt = 1124,
+	},
+};
+
 static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
 	.encp = {
 		.dvi_settings = 0xd,
@@ -816,10 +1099,12 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
 	},
 };
 
-static struct meson_hdmi_venc_vic_mode {
+struct meson_hdmi_venc_vic_mode {
 	unsigned int vic;
 	union meson_hdmi_venc_mode *mode;
-} meson_hdmi_venc_vic_modes[] = {
+};
+
+static struct meson_hdmi_venc_vic_mode meson_hdmi_venc_vic_modes[] = {
 	{ 6, &meson_hdmi_enci_mode_480i },
 	{ 7, &meson_hdmi_enci_mode_480i },
 	{ 21, &meson_hdmi_enci_mode_576i },
@@ -845,6 +1130,23 @@ static struct meson_hdmi_venc_vic_mode {
 	{ 0, NULL}, /* sentinel */
 };
 
+static struct meson_hdmi_venc_vic_mode meson_s4_hdmi_venc_vic_modes[] = {
+	{ 2, &meson_s4_hdmi_encp_mode_480p },
+	{ 3, &meson_s4_hdmi_encp_mode_480p },
+	{ 17, &meson_s4_hdmi_encp_mode_576p },
+	{ 18, &meson_s4_hdmi_encp_mode_576p },
+	{ 4, &meson_s4_hdmi_encp_mode_720p60 },
+	{ 19, &meson_s4_hdmi_encp_mode_720p50 },
+	{ 5, &meson_s4_hdmi_encp_mode_1080i60 },
+	{ 20, &meson_s4_hdmi_encp_mode_1080i50 },
+	{ 32, &meson_hdmi_encp_mode_1080p24 },
+	{ 33, &meson_hdmi_encp_mode_1080p50 },
+	{ 34, &meson_hdmi_encp_mode_1080p30 },
+	{ 31, &meson_hdmi_encp_mode_1080p50 },
+	{ 16, &meson_hdmi_encp_mode_1080p60 },
+	{ 0, NULL}, /* sentinel */
+};
+
 static signed int to_signed(unsigned int a)
 {
 	if (a <= 7)
@@ -882,6 +1184,9 @@ bool meson_venc_hdmi_supported_vic(struct meson_drm *priv, int vic)
 {
 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		vmode = meson_s4_hdmi_venc_vic_modes;
+
 	while (vmode->vic && vmode->mode) {
 		if (vmode->vic == vic)
 			return true;
@@ -921,6 +1226,9 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(struct meson_dr
 {
 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		vmode = meson_s4_hdmi_venc_vic_modes;
+
 	while (vmode->vic && vmode->mode) {
 		if (vmode->vic == vic)
 			return vmode->mode;
@@ -932,6 +1240,8 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(struct meson_dr
 
 bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic)
 {
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		return false;
 	/* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
 	if (vic == 6 || vic == 7 || /* 480i */
 	    vic == 21 || vic == 22 || /* 576i */
@@ -1957,12 +2267,19 @@ void meson_venc_enable_vsync(struct meson_drm *priv)
 		writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
 			       priv->io_base + _REG(VENC_INTCTRL));
 	}
-	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
+
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		regmap_update_bits(priv->clkctrl, CLKCTRL_SYS_CLK_EN0_REG2, BIT(4), BIT(4));
+	else
+		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
 }
 
 void meson_venc_disable_vsync(struct meson_drm *priv)
 {
-	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		regmap_update_bits(priv->clkctrl, CLKCTRL_SYS_CLK_EN0_REG2, BIT(4), 0);
+	else
+		regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);
 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
 }
 
@@ -1972,6 +2289,9 @@ void meson_venc_init(struct meson_drm *priv)
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
 		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0);
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 8);
 	} else {
 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
 		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
@@ -1981,8 +2301,10 @@ void meson_venc_init(struct meson_drm *priv)
 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
 
 	/* Disable HDMI PHY */
-	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
-
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0);
+	else
+		regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
 	/* Disable HDMI */
 	writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
 			    VPU_HDMI_ENCP_DATA_TO_HDMI, 0,

-- 
2.43.0

[PATCH 09/11] drm: meson: add vpu clk setting for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

The S4-series splits the HIU into `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
Introduce VPU clock settings specific to the Amlogic S4 SoC,
which differ from the configurations used for G12.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_vclk.c | 1018 +++++++++++++++++++++++++-----------
 1 file changed, 720 insertions(+), 298 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a942dc6a6dc23561ec26a54139b27acf8009ccb..b2707af2a5283874936658d2749cecb4ef86beb5 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -87,8 +87,11 @@
 #define CTS_VDAC_EN		BIT(4)
 #define HDMI_TX_PIXEL_EN	BIT(5)
 #define HHI_HDMI_CLK_CNTL	0x1cc /* 0x73 offset in data sheet */
-#define HDMI_TX_PIXEL_SEL_MASK	(0xf << 16)
+#define HDMI_TX_PIXEL_SEL_MASK	GENMASK(19, 16)
 #define HDMI_TX_PIXEL_SEL_SHIFT	16
+
+#define HDMI_TX_FE_SEL_MASK	GENMASK(23, 20)
+#define HDMI_TX_FE_SEL_SHIFT	20
 #define CTS_HDMI_SYS_SEL_MASK	(0x7 << 9)
 #define CTS_HDMI_SYS_DIV_MASK	(0x7f)
 #define CTS_HDMI_SYS_EN		BIT(8)
@@ -110,6 +113,30 @@
 #define HDMI_PLL_LOCK		BIT(31)
 #define HDMI_PLL_LOCK_G12A	(3 << 30)
 
+/* ANA Registers */
+/* REG_BASE:  REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_VID_CLK_CTRL	0x0c0 /* 0x30 offset in data sheet */
+#define CLKCTRL_VID_CLK_CTRL2	0x0c4 /* 0x31 offset in data sheet */
+#define CLKCTRL_VID_CLK_DIV	0x0c8 /* 0x32 offset in data sheet */
+#define CLKCTRL_VIID_CLK_DIV	0x0cc /* 0x33 offset in data sheet */
+#define CLKCTRL_VIID_CLK_CTRL	0x0d0 /* 0x34 offset in data sheet */
+
+#define CLKCTRL_VID_PLL_CLK_DIV	0x0e4 /* 0x39 offset in data sheet */
+#define CLKCTRL_HDMI_CLK_CTRL	0x0e0  /* 0x38 */
+
+/* REG_BASE:  REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPLL_CTRL0	0x1c0 /* 0x70 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL1	0x1c4 /* 0x71 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL2	0x1c8 /* 0x72 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL3	0x1cc /* 0x73 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL4	0x1d0 /* 0x74 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL5	0x1d4 /* 0x75 offset in data sheet */
+#define ANACTRL_HDMIPLL_CTRL6	0x1d8 /* 0x76 offset in data sheet */
+#define ANACTRL_HDMIPLL_STS	0x1dc /* 0x77 offset in data sheet */
+#define ANACTRL_HDMIPLL_VLOCK	0x1e4 /* 0x79 offset in data sheet */
+#define HDMI_PLL_RESET_S4	BIT(29)
+#define HDMI_PLL_LOCK_S4	(3 << 30)
+
 #define FREQ_1000_1001(_freq)	DIV_ROUND_CLOSEST(_freq * 1000, 1001)
 
 /* VID PLL Dividers */
@@ -137,8 +164,13 @@ static void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 	unsigned int shift_sel = 0;
 
 	/* Disable vid_pll output clock */
-	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
-	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
+	} else {
+		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
+		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
+	}
 
 	switch (div) {
 	case VID_PLL_DIV_2:
@@ -199,37 +231,71 @@ static void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 		break;
 	}
 
-	if (div == VID_PLL_DIV_1)
-		/* Enable vid_pll bypass to HDMI pll */
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   VID_PLL_BYPASS, VID_PLL_BYPASS);
-	else {
-		/* Disable Bypass */
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   VID_PLL_BYPASS, 0);
-		/* Clear sel */
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   3 << 16, 0);
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   VID_PLL_PRESET, 0);
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   0x7fff, 0);
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		if (div == VID_PLL_DIV_1) {
+			/* Enable vid_pll bypass to HDMI pll */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   VID_PLL_BYPASS, VID_PLL_BYPASS);
+		} else {
+			/* Disable Bypass */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   VID_PLL_BYPASS, 0);
+			/* Clear sel */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   3 << 16, 0);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, 0);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   0x7fff, 0);
+
+			/* Setup sel and val */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   3 << 16, shift_sel << 16);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, VID_PLL_PRESET);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   0x7fff, shift_val);
+
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, 0);
+		}
 
-		/* Setup sel and val */
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   3 << 16, shift_sel << 16);
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   VID_PLL_PRESET, VID_PLL_PRESET);
-		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   0x7fff, shift_val);
+		/* Enable the vid_pll output clock */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV,
+					VID_PLL_EN, VID_PLL_EN);
+	} else {
+		if (div == VID_PLL_DIV_1) {
+			/* Enable vid_pll bypass to HDMI pll */
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   VID_PLL_BYPASS, VID_PLL_BYPASS);
+		} else {
+			/* Disable Bypass */
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   VID_PLL_BYPASS, 0);
+			/* Clear sel */
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   3 << 16, 0);
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, 0);
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   0x7fff, 0);
+
+			/* Setup sel and val */
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   3 << 16, shift_sel << 16);
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, VID_PLL_PRESET);
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   0x7fff, shift_val);
+
+			regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
+					   VID_PLL_PRESET, 0);
+		}
 
+		/* Enable the vid_pll output clock */
 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				   VID_PLL_PRESET, 0);
+					VID_PLL_EN, VID_PLL_EN);
 	}
-
-	/* Enable the vid_pll output clock */
-	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
-				VID_PLL_EN, VID_PLL_EN);
 }
 
 /*
@@ -287,56 +353,117 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 			((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
 			10, 0);
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x3b01047b);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x1b01047b);
+
+		/* Poll for lock bit */
+		regmap_read_poll_timeout(priv->hhi, ANACTRL_HDMIPLL_CTRL0, val,
+			((val & HDMI_PLL_LOCK) == HDMI_PLL_LOCK),
+			10, 0);
 	}
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		/* Disable VCLK2 */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, VCLK2_EN, 0);
 
-	/* Disable VCLK2 */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+		/* Setup vid_pll to /1 */
+		meson_vid_pll_set(priv, VID_PLL_DIV_1);
 
-	/* Setup vid_pll to /1 */
-	meson_vid_pll_set(priv, VID_PLL_DIV_1);
+		/* Setup the VCLK2 divider value to achieve 27MHz */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV,
+					VCLK2_DIV_MASK, (55 - 1));
 
-	/* Setup the VCLK2 divider value to achieve 27MHz */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
-				VCLK2_DIV_MASK, (55 - 1));
+		/* select vid_pll for vclk2 */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL,
+					VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
 
-	/* select vid_pll for vclk2 */
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+		/* enable vclk2 gate */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, VCLK2_EN, VCLK2_EN);
+
+		/* select vclk_div1 for enci */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
+		/* select vclk_div1 for vdac */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV,
+					CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
+
+		/* release vclk2_div_reset and enable vclk2_div */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV,
+					VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
+
+		/* enable vclk2_div1 gate */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL,
+					VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+		/* reset vclk2 */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL,
+					VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL,
+					VCLK2_SOFT_RESET, 0);
+
+		/* enable enci_clk */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2,
+					CTS_ENCI_EN, CTS_ENCI_EN);
+		/* enable vdac_clk */
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2,
+					CTS_VDAC_EN, CTS_VDAC_EN);
+
+	} else {
+		/* Disable VCLK2 */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+		/* Setup vid_pll to /1 */
+		meson_vid_pll_set(priv, VID_PLL_DIV_1);
+
+		/* Setup the VCLK2 divider value to achieve 27MHz */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+					VCLK2_DIV_MASK, (55 - 1));
+
+		/* select vid_pll for vclk2 */
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+			regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+						VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+		else
+			regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+						VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
+
+		/* enable vclk2 gate */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+		/* select vclk_div1 for enci */
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
+		/* select vclk_div1 for vdac */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+					CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
+
+		/* release vclk2_div_reset and enable vclk2_div */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+					VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
+
+		/* enable vclk2_div1 gate */
 		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
-					VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
-	else
+					VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+		/* reset vclk2 */
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+					VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
-					VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
-
-	/* enable vclk2 gate */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
-
-	/* select vclk_div1 for enci */
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
-	/* select vclk_div1 for vdac */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
-				CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
-
-	/* release vclk2_div_reset and enable vclk2_div */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
-				VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
-
-	/* enable vclk2_div1 gate */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
-				VCLK2_DIV1_EN, VCLK2_DIV1_EN);
-
-	/* reset vclk2 */
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
-				VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
-				VCLK2_SOFT_RESET, 0);
-
-	/* enable enci_clk */
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
-				CTS_ENCI_EN, CTS_ENCI_EN);
-	/* enable vdac_clk */
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
-				CTS_VDAC_EN, CTS_VDAC_EN);
+					VCLK2_SOFT_RESET, 0);
+
+		/* enable enci_clk */
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+					CTS_ENCI_EN, CTS_ENCI_EN);
+		/* enable vdac_clk */
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+					CTS_VDAC_EN, CTS_VDAC_EN);
+	}
 }
 
 enum {
@@ -357,6 +484,8 @@ enum {
 	MESON_VCLK_HDMI_594000,
 /* 2970 /1 /1 /1 /5 /1  => /1 /2 */
 	MESON_VCLK_HDMI_594000_YUV420,
+/* 4320 /4 /4 /1 /5 /1  => /2 /2 */
+	MESON_VCLK_HDMI_27000,
 };
 
 struct meson_vclk_params {
@@ -467,6 +596,18 @@ struct meson_vclk_params {
 		.vid_pll_div = VID_PLL_DIV_5,
 		.vclk_div = 1,
 	},
+	[MESON_VCLK_HDMI_27000] = {
+		.pll_freq = 4320000,
+		.phy_freq = 270000,
+		.vclk_freq = 54000,
+		.venc_freq = 27000,
+		.pixel_freq = 27000,
+		.pll_od1 = 4,
+		.pll_od2 = 4,
+		.pll_od3 = 1,
+		.vid_pll_div = VID_PLL_DIV_5,
+		.vclk_div = 1,
+	},
 	{ /* sentinel */ },
 };
 
@@ -487,136 +628,226 @@ static inline unsigned int pll_od_to_reg(unsigned int od)
 	return 0;
 }
 
-static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
+static void gxbb_pll_set_params(struct meson_drm *priv, unsigned int m,
 				      unsigned int frac, unsigned int od1,
 				      unsigned int od2, unsigned int od3)
 {
 	unsigned int val;
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
-		if (frac)
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
-				     0x00004000 | frac);
-		else
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
-				     0x00000000);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
+	if (frac)
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
+			     0x00004000 | frac);
+	else
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
+			     0x00000000);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+
+	/* Enable and unreset */
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+			   0x7 << 28, HHI_HDMI_PLL_CNTL_EN);
+
+	/* Poll for lock bit */
+	regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+				 val, (val & HDMI_PLL_LOCK), 10, 0);
+
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+				3 << 16, pll_od_to_reg(od1) << 16);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+				3 << 22, pll_od_to_reg(od2) << 22);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+				3 << 18, pll_od_to_reg(od3) << 18);
+}
 
-		/* Enable and unreset */
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				   0x7 << 28, HHI_HDMI_PLL_CNTL_EN);
+static void gxm_pll_set_params(struct meson_drm *priv, unsigned int m,
+				      unsigned int frac, unsigned int od1,
+				      unsigned int od2, unsigned int od3)
+{
+	unsigned int val;
 
-		/* Poll for lock bit */
-		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-					 val, (val & HDMI_PLL_LOCK), 10, 0);
-	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 
-		/* Reset PLL */
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				HDMI_PLL_RESET, HDMI_PLL_RESET);
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				HDMI_PLL_RESET, 0);
+	/* Reset PLL */
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+			HDMI_PLL_RESET, HDMI_PLL_RESET);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+			HDMI_PLL_RESET, 0);
 
-		/* Poll for lock bit */
-		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
-				(val & HDMI_PLL_LOCK), 10, 0);
-	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
+	/* Poll for lock bit */
+	regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
+			(val & HDMI_PLL_LOCK), 10, 0);
 
-		/* Enable and reset */
-		/* TODO: add specific macro for g12a here */
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				   0x3 << 28, 0x3 << 28);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
+				3 << 21, pll_od_to_reg(od1) << 21);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
+				3 << 23, pll_od_to_reg(od2) << 23);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
+				3 << 19, pll_od_to_reg(od3) << 19);
+}
 
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
-		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
+static void g12a_pll_set_params(struct meson_drm *priv, unsigned int m,
+				      unsigned int frac, unsigned int od1,
+				      unsigned int od2, unsigned int od3)
+{
+	unsigned int val;
+
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
+
+	/* Enable and reset */
+	/* TODO: add specific macro for g12a here */
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+			   0x3 << 28, 0x3 << 28);
 
-		/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
-		if (m >= 0xf7) {
-			if (frac < 0x10000) {
-				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
-							0x6a685c00);
-				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
-							0x11551293);
-			} else {
-				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
-							0xea68dc00);
-				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
-							0x65771290);
-			}
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
+	regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
+
+	/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
+	if (m >= 0xf7) {
+		if (frac < 0x10000) {
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+						0x6a685c00);
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+						0x11551293);
 		} else {
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
-			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+						0xea68dc00);
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+						0x65771290);
 		}
-
-		do {
-			/* Reset PLL */
-			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-					HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
-
-			/* UN-Reset PLL */
-			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-					HDMI_PLL_RESET_G12A, 0);
-
-			/* Poll for lock bits */
-			if (!regmap_read_poll_timeout(priv->hhi,
-						      HHI_HDMI_PLL_CNTL, val,
-						      ((val & HDMI_PLL_LOCK_G12A)
-						        == HDMI_PLL_LOCK_G12A),
-						      10, 100))
-				break;
-		} while(1);
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
+	} else {
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
 	}
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-				3 << 16, pll_od_to_reg(od1) << 16);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
-				3 << 21, pll_od_to_reg(od1) << 21);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+	do {
+		/* Reset PLL */
 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				3 << 16, pll_od_to_reg(od1) << 16);
+				HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-				3 << 22, pll_od_to_reg(od2) << 22);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
-				3 << 23, pll_od_to_reg(od2) << 23);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+		/* UN-Reset PLL */
 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-				3 << 18, pll_od_to_reg(od2) << 18);
+				HDMI_PLL_RESET_G12A, 0);
+
+		/* Poll for lock bits */
+		if (!regmap_read_poll_timeout(priv->hhi,
+					      HHI_HDMI_PLL_CNTL, val,
+					      ((val & HDMI_PLL_LOCK_G12A)
+					      == HDMI_PLL_LOCK_G12A),
+					      10, 100))
+			break;
+	} while (1);
 
-	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-				3 << 18, pll_od_to_reg(od3) << 18);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
-		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
-				3 << 19, pll_od_to_reg(od3) << 19);
-	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
-		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+				3 << 16, pll_od_to_reg(od1) << 16);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+					3 << 18, pll_od_to_reg(od2) << 18);
+	regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+				3 << 20, pll_od_to_reg(od3) << 20);
+}
+
+static void s4_pll_set_params(struct meson_drm *priv, unsigned int m,
+				      unsigned int frac, unsigned int od1,
+				      unsigned int od2, unsigned int od3)
+{
+	unsigned int val;
+
+	DRM_DEBUG_DRIVER("%s: m = %d, frac = %d, od1 = %d, od2 = %d, od3 = %d\n",
+			__func__, m, frac, od1, od2, od3);
+
+	regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | m);
+
+	/* Enable and reset */
+	/* TODO: add specific macro for g12a here */
+	regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
+			   0x3 << 28, 0x3 << 28);
+
+	regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL1, frac);
+	regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+
+	/* S4 HDMI PLL Needs specific parameters for 5.4GHz */
+	if (m >= 0xf7) {
+		if (frac < 0x10000) {
+			regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3,
+						0x6a685c00);
+			regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4,
+						0x11551293);
+		} else {
+			regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3,
+						0x6a685c00);
+			regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4,
+						0x44331290);
+		}
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39272008);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+	} else {
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39272008);
+		regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+	}
+
+	do {
+		//todo, need confir rst and lock bit
+		/* Reset PLL */
+		regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
+				HDMI_PLL_RESET_S4, HDMI_PLL_RESET_S4);
+
+		/* UN-Reset PLL */
+		regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
+				HDMI_PLL_RESET_S4, 0);
+
+		/* Poll for lock bits */
+		if (!regmap_read_poll_timeout(priv->hhi,
+					      ANACTRL_HDMIPLL_CTRL0, val,
+					      ((val & HDMI_PLL_LOCK_S4)
+					      == HDMI_PLL_LOCK_S4),
+					      10, 100))
+			break;
+	} while (1);
+
+	regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
+				3 << 16, pll_od_to_reg(od1) << 16);
+	regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
+					3 << 18, pll_od_to_reg(od2) << 18);
+	regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0,
 				3 << 20, pll_od_to_reg(od3) << 20);
 }
 
+static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
+				      unsigned int frac, unsigned int od1,
+				      unsigned int od2, unsigned int od3)
+{
+	switch (priv->compat) {
+	case VPU_COMPATIBLE_GXBB:
+		gxbb_pll_set_params(priv, m, frac, od1, od2, od3);
+		break;
+	case VPU_COMPATIBLE_GXM:
+	case VPU_COMPATIBLE_GXL:
+		gxm_pll_set_params(priv, m, frac, od1, od2, od3);
+		break;
+	case VPU_COMPATIBLE_G12A:
+		g12a_pll_set_params(priv, m, frac, od1, od2, od3);
+		break;
+	case VPU_COMPATIBLE_S4:
+		s4_pll_set_params(priv, m, frac, od1, od2, od3);
+		break;
+	default:
+		break;
+	}
+}
+
 #define XTAL_FREQ 24000
 
 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
@@ -632,6 +863,7 @@ static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
 #define HDMI_FRAC_MAX_GXBB	4096
 #define HDMI_FRAC_MAX_GXL	1024
 #define HDMI_FRAC_MAX_G12A	131072
+#define HDMI_FRAC_MAX_S4	131072
 
 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
 					    unsigned int m,
@@ -651,6 +883,9 @@ static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 		frac_max = HDMI_FRAC_MAX_G12A;
 
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		frac_max = HDMI_FRAC_MAX_S4;
+
 	/* We can have a perfect match !*/
 	if (pll_freq / m == parent_freq &&
 	    pll_freq % m == 0)
@@ -688,6 +923,12 @@ static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
 			return false;
 		if (frac >= HDMI_FRAC_MAX_G12A)
 			return false;
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		/* Empiric supported min/max dividers */
+		if (m < 106 || m > 247)
+			return false;
+		if (frac >= HDMI_FRAC_MAX_S4)
+			return false;
 	}
 
 	return true;
@@ -813,14 +1054,22 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 {
 	unsigned int m = 0, frac = 0;
 
-	/* Set HDMI-TX sys clock */
-	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			   CTS_HDMI_SYS_SEL_MASK, 0);
-	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			   CTS_HDMI_SYS_DIV_MASK, 0);
-	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			   CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
-
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				CTS_HDMI_SYS_SEL_MASK, 0);
+		regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				   CTS_HDMI_SYS_DIV_MASK, 0);
+		regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				   CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
+	} else {
+		/* Set HDMI-TX sys clock */
+		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				   CTS_HDMI_SYS_SEL_MASK, 0);
+		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				   CTS_HDMI_SYS_DIV_MASK, 0);
+		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				   CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
+	}
 	/* Set HDMI PLL rate */
 	if (!od1 && !od2 && !od3) {
 		meson_hdmi_pll_generic_set(priv, pll_base_freq);
@@ -875,6 +1124,22 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 			break;
 		}
 
+		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		switch (pll_base_freq) {
+		case 2970000:
+			m = 0x7b;
+			frac = vic_alternate_clock ? 0x140b4 : 0x18000;
+			break;
+		case 4320000:
+			m = vic_alternate_clock ? 0xb3 : 0xb4;
+			frac = vic_alternate_clock ? 0x1a3ee : 0;
+			break;
+		case 5940000:
+			m = 0xf7;
+			frac = vic_alternate_clock ? 0x8148 : 0x10000;
+			break;
+		}
 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 	}
 
@@ -882,146 +1147,303 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 	meson_vid_pll_set(priv, vid_pll_div);
 
 	/* Set VCLK div */
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-			   VCLK_SEL_MASK, 0);
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-			   VCLK_DIV_MASK, vclk_div - 1);
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+				   VCLK_SEL_MASK, 0);
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+				   VCLK_DIV_MASK, vclk_div - 1);
+	} else {
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+				   VCLK_SEL_MASK, 0);
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+				   VCLK_DIV_MASK, vclk_div - 1);
+	}
 
 	/* Set HDMI-TX source */
 	switch (hdmi_tx_div) {
 	case 1:
-		/* enable vclk_div1 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV1_EN, VCLK_DIV1_EN);
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			/* enable vclk_div1 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV1_EN, VCLK_DIV1_EN);
+
+			/* select vclk_div1 for HDMI-TX */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+					   HDMI_TX_PIXEL_SEL_MASK, 0);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+						HDMI_TX_FE_SEL_MASK, 0);
+		} else {
+			/* enable vclk_div1 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV1_EN, VCLK_DIV1_EN);
 
-		/* select vclk_div1 for HDMI-TX */
-		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-				   HDMI_TX_PIXEL_SEL_MASK, 0);
+			/* select vclk_div1 for HDMI-TX */
+			regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+					   HDMI_TX_PIXEL_SEL_MASK, 0);
+		}
 		break;
 	case 2:
-		/* enable vclk_div2 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV2_EN, VCLK_DIV2_EN);
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			/* enable vclk_div2 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV2_EN, VCLK_DIV2_EN);
+
+			/* select vclk_div2 for HDMI-TX */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_FE_SEL_MASK, 1 << HDMI_TX_FE_SEL_SHIFT);
+		} else {
+			/* enable vclk_div2 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV2_EN, VCLK_DIV2_EN);
 
-		/* select vclk_div2 for HDMI-TX */
-		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
+			/* select vclk_div2 for HDMI-TX */
+			regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
+		}
 		break;
 	case 4:
-		/* enable vclk_div4 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV4_EN, VCLK_DIV4_EN);
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			/* enable vclk_div4 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV4_EN, VCLK_DIV4_EN);
+
+			/* select vclk_div4 for HDMI-TX */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_FE_SEL_MASK, 2 << HDMI_TX_FE_SEL_SHIFT);
+		} else {
+			/* enable vclk_div4 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV4_EN, VCLK_DIV4_EN);
 
-		/* select vclk_div4 for HDMI-TX */
-		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
+			/* select vclk_div4 for HDMI-TX */
+			regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
+		}
 		break;
 	case 6:
-		/* enable vclk_div6 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV6_EN, VCLK_DIV6_EN);
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			/* enable vclk_div6 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV6_EN, VCLK_DIV6_EN);
+
+			/* select vclk_div6 for HDMI-TX */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_FE_SEL_MASK, 3 << HDMI_TX_FE_SEL_SHIFT);
+		} else {
+			/* enable vclk_div6 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV6_EN, VCLK_DIV6_EN);
 
-		/* select vclk_div6 for HDMI-TX */
-		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
+			/* select vclk_div6 for HDMI-TX */
+			regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
+		}
 		break;
 	case 12:
-		/* enable vclk_div12 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV12_EN, VCLK_DIV12_EN);
+		if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+			/* enable vclk_div12 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV12_EN, VCLK_DIV12_EN);
+
+			/* select vclk_div12 for HDMI-TX */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
+			regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL,
+				HDMI_TX_FE_SEL_MASK, 4 << HDMI_TX_FE_SEL_SHIFT);
+		} else {
+			/* enable vclk_div12 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV12_EN, VCLK_DIV12_EN);
 
-		/* select vclk_div12 for HDMI-TX */
-		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
-			HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
+			/* select vclk_div12 for HDMI-TX */
+			regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
+				HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
+		}
 		break;
 	}
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2,
+				   HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
+	else
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 				   HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 
 	/* Set ENCI/ENCP Source */
-	switch (venc_div) {
-	case 1:
-		/* enable vclk_div1 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV1_EN, VCLK_DIV1_EN);
-
-		if (hdmi_use_enci)
-			/* select vclk_div1 for enci */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-					   CTS_ENCI_SEL_MASK, 0);
-		else
-			/* select vclk_div1 for encp */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-					   CTS_ENCP_SEL_MASK, 0);
-		break;
-	case 2:
-		/* enable vclk_div2 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV2_EN, VCLK_DIV2_EN);
-
-		if (hdmi_use_enci)
-			/* select vclk_div2 for enci */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
-		else
-			/* select vclk_div2 for encp */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
-		break;
-	case 4:
-		/* enable vclk_div4 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV4_EN, VCLK_DIV4_EN);
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		switch (venc_div) {
+		case 1:
+			/* enable vclk_div1 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV1_EN, VCLK_DIV1_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div1 for enci */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+						   CTS_ENCI_SEL_MASK, 0);
+			else
+				/* select vclk_div1 for encp */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+						   CTS_ENCP_SEL_MASK, 0);
+			break;
+		case 2:
+			/* enable vclk_div2 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV2_EN, VCLK_DIV2_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div2 for enci */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div2 for encp */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 4:
+			/* enable vclk_div4 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV4_EN, VCLK_DIV4_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div4 for enci */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div4 for encp */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 6:
+			/* enable vclk_div6 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV6_EN, VCLK_DIV6_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div6 for enci */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div6 for encp */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 12:
+			/* enable vclk_div12 gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL,
+					   VCLK_DIV12_EN, VCLK_DIV12_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div12 for enci */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div12 for encp */
+				regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV,
+					CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
+			break;
+		}
 
 		if (hdmi_use_enci)
-			/* select vclk_div4 for enci */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
+			/* Enable ENCI clock gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2,
+					   CTS_ENCI_EN, CTS_ENCI_EN);
 		else
-			/* select vclk_div4 for encp */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
-		break;
-	case 6:
-		/* enable vclk_div6 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV6_EN, VCLK_DIV6_EN);
+			/* Enable ENCP clock gate */
+			regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2,
+					   CTS_ENCP_EN, CTS_ENCP_EN);
+
+		regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, VCLK_EN, VCLK_EN);
+	} else {
+		switch (venc_div) {
+		case 1:
+			/* enable vclk_div1 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV1_EN, VCLK_DIV1_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div1 for enci */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						   CTS_ENCI_SEL_MASK, 0);
+			else
+				/* select vclk_div1 for encp */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						   CTS_ENCP_SEL_MASK, 0);
+			break;
+		case 2:
+			/* enable vclk_div2 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV2_EN, VCLK_DIV2_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div2 for enci */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div2 for encp */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 4:
+			/* enable vclk_div4 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV4_EN, VCLK_DIV4_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div4 for enci */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div4 for encp */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 6:
+			/* enable vclk_div6 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV6_EN, VCLK_DIV6_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div6 for enci */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div6 for encp */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
+			break;
+		case 12:
+			/* enable vclk_div12 gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
+					   VCLK_DIV12_EN, VCLK_DIV12_EN);
+
+			if (hdmi_use_enci)
+				/* select vclk_div12 for enci */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
+			else
+				/* select vclk_div12 for encp */
+				regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
+						CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
+			break;
+		}
 
 		if (hdmi_use_enci)
-			/* select vclk_div6 for enci */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
+			/* Enable ENCI clock gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+					   CTS_ENCI_EN, CTS_ENCI_EN);
 		else
-			/* select vclk_div6 for encp */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
-		break;
-	case 12:
-		/* enable vclk_div12 gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
-				   VCLK_DIV12_EN, VCLK_DIV12_EN);
+			/* Enable ENCP clock gate */
+			regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+					   CTS_ENCP_EN, CTS_ENCP_EN);
 
-		if (hdmi_use_enci)
-			/* select vclk_div12 for enci */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
-		else
-			/* select vclk_div12 for encp */
-			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
-				CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
-		break;
+		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 	}
-
-	if (hdmi_use_enci)
-		/* Enable ENCI clock gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
-				   CTS_ENCI_EN, CTS_ENCI_EN);
-	else
-		/* Enable ENCP clock gate */
-		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
-				   CTS_ENCP_EN, CTS_ENCP_EN);
-
-	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 }
 
 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,

-- 
2.43.0

[PATCH 10/11] drm: meson: add CVBS support for S4

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add support for Composite Video Baseband Signal (CVBS)
in the Meson encoder driver for the Amlogic S4 SoC.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 drivers/gpu/drm/meson/meson_encoder_cvbs.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
index d1191de855d910f9845bf2d5aef336e391982ba2..45ed800173c1754b23fdc8b53e9487530bcae5a3 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
@@ -30,6 +30,10 @@
 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
 #define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */
 
+/* ANA VDAC Registers */
+#define ANACTRL_VDAC_CTRL0	0x2c0 /* 0xb0 offset in data sheet */
+#define ANACTRL_VDAC_CTRL1	0x2c4 /* 0xb1 offset in data sheet */
+
 struct meson_encoder_cvbs {
 	struct drm_encoder	encoder;
 	struct drm_bridge	bridge;
@@ -187,6 +191,9 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge,
 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
 		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0x406802);
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0xc4);
 	}
 }
 
@@ -201,6 +208,9 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge,
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
 		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) {
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0);
+		regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0);
 	} else {
 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
 		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);

-- 
2.43.0

[PATCH 11/11] arm64: dts: amlogic: s4: add DRM support [1/1]

[Ao Xu via B4 Relay]

From: Ao Xu <ao.xu@amlogic.com>

Add Device Tree support for the DRM subsystem on the Amlogic S4 SoC.
Enable nodes for canvas, vpu, and HDMI controllers.
Enable nodes for CVBS and HDMI bridge connector components.

Signed-off-by: Ao Xu <ao.xu@amlogic.com>
---
 .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts     |  39 +++++++
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi          | 121 +++++++++++++++++++++
 2 files changed, 160 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
index 6730c44642d2910d42ec0c4adf49fefc3514dbec..e40206192ac0f7b80da23e629aa3044c04f7e969 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
@@ -129,6 +129,27 @@ vddcpu: regulator-vddcpu {
 				<699000 98>,
 				<689000 100>;
 	};
+
+	cvbs-connector {
+		compatible = "composite-video-connector";
+
+		port {
+			cvbs_connector_in: endpoint {
+				remote-endpoint = <&cvbs_vdac_out>;
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
 };
 
 &pwm_ef {
@@ -235,3 +256,21 @@ &ethmac {
 	phy-handle = <&internal_ephy>;
 	phy-mode = "rmii";
 };
+
+&cvbs_vdac_port {
+	cvbs_vdac_out: endpoint {
+		remote-endpoint = <&cvbs_connector_in>;
+	};
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index 957577d986c0675a503115e1ccbc4387c2051620..ce4a24f0880c09cf4fd06d2046b520335d62a6cd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/meson-s4-gpio.h>
 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
+#include <dt-bindings/reset/amlogic,meson-s4-reset.h>
 #include <dt-bindings/power/meson-s4-power.h>
 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
 
@@ -102,6 +103,50 @@ apb4: bus@fe000000 {
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
 
+			dmc: bus@36000 {
+				compatible = "simple-bus";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges = <0x0 0x0 0x0 0x36000 0x0 0x2000>;
+
+				canvas: video-lut@48 {
+					compatible = "amlogic,canvas";
+					reg = <0x0 0x48 0x0 0x14>;
+				};
+			};
+
+			hdmi_tx: hdmi-tx@300000 {
+				compatible = "amlogic,meson-s4-dw-hdmi";
+				reg = <0x0 0x300000 0x0 0x10000>;
+				interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
+				resets = <&reset RESET_HDMITX_APB>,
+					 <&reset RESET_HDMITXPHY>,
+					 <&reset RESET_HDMI_TX>;
+				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+				clocks = <&clkc_periphs CLKID_HDMI>,
+					 <&clkc_periphs CLKID_HDMITX_APB>,
+					 <&clkc_periphs CLKID_VPU_INTR>;
+				clock-names = "isfr", "iahb", "venci";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#sound-dai-cells = <0>;
+				status = "disabled";
+
+				/* VPU VENC Input */
+				hdmi_tx_venc_port: port@0 {
+					reg = <0>;
+
+					hdmi_tx_in: endpoint {
+						remote-endpoint = <&hdmi_tx_out>;
+					};
+				};
+
+				/* TMDS Output */
+				hdmi_tx_tmds_port: port@1 {
+					reg = <1>;
+				};
+			};
+
 			clkc_periphs: clock-controller@0 {
 				compatible = "amlogic,s4-peripherals-clkc";
 				reg = <0x0 0x0 0x0 0x49c>;
@@ -584,6 +629,24 @@ mux {
 					};
 				};
 
+				hdmitx_hpd_pins: hdmitx-hpd {
+					mux {
+						groups = "hdmitx_hpd_in";
+						function = "hdmitx";
+						bias-disable;
+					};
+				};
+
+				hdmitx_ddc_pins: hdmitx-ddc {
+					mux {
+						groups = "hdmitx_sda",
+								"hdmitx_sck";
+						function = "hdmitx";
+						bias-disable;
+						drive-strength-microamp = <4000>;
+					};
+				};
+
 			};
 
 			gpio_intc: interrupt-controller@4080 {
@@ -848,5 +911,63 @@ emmc: mmc@fe08c000 {
 			no-sd;
 			status = "disabled";
 		};
+
+		vpu: vpu@ff000000 {
+			compatible = "amlogic,meson-s4-vpu";
+			reg = <0x0 0xff000000 0x0 0x40000>,
+				  <0x0 0xfe008000 0x0 0x2000>,
+				  <0x0 0xfe000000 0x0 0x2000>,
+				  <0x0 0xfe00c000 0x0 0x0800>,
+				  <0x0 0xfe010000 0x0 0x0100>;
+			reg-names = "vpu", "hhi", "clkctrl", "pwrctrl", "sysctrl";
+			interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			amlogic,canvas = <&canvas>;
+			power-domains = <&pwrc PWRC_S4_VPU_HDMI_ID>;
+
+			clocks = <&clkc_periphs CLKID_VPU>,
+				 <&clkc_periphs CLKID_VAPB>;
+			clock-names = "vpu", "vapb";
+
+			/*
+			 * VPU clocking is provided by two identical clock paths
+			 * VPU_0 and VPU_1 muxed to a single clock by a glitch
+			 * free mux to safely change frequency while running.
+			 * Same for VAPB but with a final gate after the glitch free mux.
+			 */
+			assigned-clocks = <&clkc_periphs CLKID_VPU_0_SEL>,
+					  <&clkc_periphs CLKID_VPU_0>,
+					  <&clkc_periphs CLKID_VPU>, /* Glitch free mux */
+					  <&clkc_periphs CLKID_VAPB_0_SEL>,
+					  <&clkc_periphs CLKID_VAPB_0>,
+					  <&clkc_periphs CLKID_VAPB>; /* Glitch free mux */
+			assigned-clock-parents = <&clkc_periphs CLKID_FCLK_DIV3>,
+						 <0>, /* Do Nothing */
+						 <&clkc_periphs CLKID_VPU_0>,
+						 <&clkc_periphs CLKID_FCLK_DIV4>,
+						 <0>, /* Do Nothing */
+						 <&clkc_periphs CLKID_VAPB_0>;
+			assigned-clock-rates = <0>, /* Do Nothing */
+					       <666666666>,
+					       <0>, /* Do Nothing */
+					       <0>, /* Do Nothing */
+					       <250000000>,
+					       <0>; /* Do Nothing */
+
+			/* CVBS VDAC output port */
+			cvbs_vdac_port: port@0 {
+				reg = <0>;
+			};
+
+			/* HDMI-TX output port */
+			hdmi_tx_port: port@1 {
+				reg = <1>;
+
+				hdmi_tx_out: endpoint {
+					remote-endpoint = <&hdmi_tx_in>;
+				};
+			};
+		};
 	};
 };

-- 
2.43.0

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Neil Armstrong]

Hi,

On 10/01/2025 06:39, Ao Xu via B4 Relay wrote:
> This patch series adds DRM support for the Amlogic S4-series SoCs.
> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
> 
> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>    As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>    requiring modifications to the driver to handle this new access method.
> 3 The register addresses for the video1 and video2 planes have been updated in the S4 hardware,
>    and the DRM driver has been adapted accordingly.
> 4 The OSD, VIU, and VPP components remain unchanged and are consistent with the G12-series.

Thanks a lot for this high quality changeset, happy to see DRM support for a new SoC !

I'll review it carefully next week.

Neil

> 
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
> Ao Xu (11):
>        dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller
>        dt-bindings: display: meson-vpu: Add compatible for S4 display controller
>        drm: meson: add S4 compatible for DRM driver
>        drm: meson: add primary and overlay plane support for S4
>        drm: meson: update VIU and VPP support for S4
>        drm: meson: add meson_dw_hdmi support for S4
>        drm: meson: change api call parameter
>        drm: meson: add hdmitx vmode timing support for S4
>        drm: meson: add vpu clk setting for S4
>        drm: meson: add CVBS support for S4
>        arm64: dts: amlogic: s4: add DRM support [1/1]
> 
>   .../bindings/display/amlogic,meson-dw-hdmi.yaml    |    1 +
>   .../bindings/display/amlogic,meson-vpu.yaml        |   48 +-
>   .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts     |   39 +
>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |  121 +++
>   drivers/gpu/drm/meson/meson_crtc.c                 |   90 +-
>   drivers/gpu/drm/meson/meson_drv.c                  |  127 ++-
>   drivers/gpu/drm/meson/meson_drv.h                  |    6 +
>   drivers/gpu/drm/meson/meson_dw_hdmi.c              |  244 ++++-
>   drivers/gpu/drm/meson/meson_dw_hdmi.h              |  126 +++
>   drivers/gpu/drm/meson/meson_encoder_cvbs.c         |   10 +
>   drivers/gpu/drm/meson/meson_encoder_hdmi.c         |   19 +-
>   drivers/gpu/drm/meson/meson_overlay.c              |    7 +-
>   drivers/gpu/drm/meson/meson_plane.c                |   24 +-
>   drivers/gpu/drm/meson/meson_registers.h            |   17 +
>   drivers/gpu/drm/meson/meson_vclk.c                 | 1018 ++++++++++++++------
>   drivers/gpu/drm/meson/meson_venc.c                 |  346 ++++++-
>   drivers/gpu/drm/meson/meson_venc.h                 |    4 +-
>   drivers/gpu/drm/meson/meson_viu.c                  |    9 +-
>   drivers/gpu/drm/meson/meson_vpp.c                  |   12 +-
>   19 files changed, 1865 insertions(+), 403 deletions(-)
> ---
> base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
> change-id: 20250110-drm-s4-c96c88be52e4
> 
> Best regards,

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Rob Herring (Arm)]

On Fri, 10 Jan 2025 13:39:50 +0800, Ao Xu wrote:
> This patch series adds DRM support for the Amlogic S4-series SoCs.
> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
> 
> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>   As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>   requiring modifications to the driver to handle this new access method.
> 3 The register addresses for the video1 and video2 planes have been updated in the S4 hardware,
>   and the DRM driver has been adapted accordingly.
> 4 The OSD, VIU, and VPP components remain unchanged and are consistent with the G12-series.
> 
> Signed-off-by: Ao Xu <ao.xu@amlogic.com>
> ---
> Ao Xu (11):
>       dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller
>       dt-bindings: display: meson-vpu: Add compatible for S4 display controller
>       drm: meson: add S4 compatible for DRM driver
>       drm: meson: add primary and overlay plane support for S4
>       drm: meson: update VIU and VPP support for S4
>       drm: meson: add meson_dw_hdmi support for S4
>       drm: meson: change api call parameter
>       drm: meson: add hdmitx vmode timing support for S4
>       drm: meson: add vpu clk setting for S4
>       drm: meson: add CVBS support for S4
>       arm64: dts: amlogic: s4: add DRM support [1/1]
> 
>  .../bindings/display/amlogic,meson-dw-hdmi.yaml    |    1 +
>  .../bindings/display/amlogic,meson-vpu.yaml        |   48 +-
>  .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts     |   39 +
>  arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |  121 +++
>  drivers/gpu/drm/meson/meson_crtc.c                 |   90 +-
>  drivers/gpu/drm/meson/meson_drv.c                  |  127 ++-
>  drivers/gpu/drm/meson/meson_drv.h                  |    6 +
>  drivers/gpu/drm/meson/meson_dw_hdmi.c              |  244 ++++-
>  drivers/gpu/drm/meson/meson_dw_hdmi.h              |  126 +++
>  drivers/gpu/drm/meson/meson_encoder_cvbs.c         |   10 +
>  drivers/gpu/drm/meson/meson_encoder_hdmi.c         |   19 +-
>  drivers/gpu/drm/meson/meson_overlay.c              |    7 +-
>  drivers/gpu/drm/meson/meson_plane.c                |   24 +-
>  drivers/gpu/drm/meson/meson_registers.h            |   17 +
>  drivers/gpu/drm/meson/meson_vclk.c                 | 1018 ++++++++++++++------
>  drivers/gpu/drm/meson/meson_venc.c                 |  346 ++++++-
>  drivers/gpu/drm/meson/meson_venc.h                 |    4 +-
>  drivers/gpu/drm/meson/meson_viu.c                  |    9 +-
>  drivers/gpu/drm/meson/meson_vpp.c                  |   12 +-
>  19 files changed, 1865 insertions(+), 403 deletions(-)
> ---
> base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
> change-id: 20250110-drm-s4-c96c88be52e4
> 
> Best regards,
> --
> Ao Xu <ao.xu@amlogic.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/amlogic/' for 20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com:

arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dtb: vpu@ff000000: reg: [[0, 4278190080, 0, 262144], [0, 4261445632, 0, 8192], [0, 4261412864, 0, 8192], [0, 4261462016, 0, 2048], [0, 4261478400, 0, 256]] is too long
	from schema $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dtb: vpu@ff000000: reg-names: ['vpu', 'hhi', 'clkctrl', 'pwrctrl', 'sysctrl'] is too long
	from schema $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dtb: vpu@ff000000: reg-names:3: 'pwctrl' was expected
	from schema $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dtb: vpu@ff000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Martin Blumenstingl]

Hello,

On Fri, Jan 10, 2025 at 6:39 AM Ao Xu via B4 Relay
<devnull+ao.xu.amlogic.com@kernel.org> wrote:
>
> This patch series adds DRM support for the Amlogic S4-series SoCs.
> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
Thanks for your patches. With this mail I'll try to summarize my
understanding of the situation with the drm/meson driver as I'm not
sure how familiar you are with previous discussions.

> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>   As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
Jerome has already commented on patch 3/11 that this mixes in too many
IP blocks into one driver.
This is not a new situation, the existing code is doing exactly the same.

Jerome has previously sent a series which started "an effort to remove
the use HHI syscon" [0] from the drm/meson hdmi driver.
In the same mail he further notes: "[the patchset] stops short of
making any controversial DT changes. To decouple the HDMI
phy driver and main DRM driver, allowing the PHY to get hold of its
registers, I believe a DT ABI break is inevitable. Ideally the
register region of the PHY within the HHI should provided, not the
whole HHI. That's pain for another day ..."

For now I'm assuming you're familiar with device-tree ABI.
If not then please let us know so we can elaborate further on this.

My own notes for meson_dw_hdmi.c are:
- we should not program HHI_HDMI_CLK_CNTL directly but go through CCF
(common clock framework) instead (we should already have the driver
for this in place)
- we should not program HHI_MEM_PD_REG0 directly but go through the
genpd/pmdomain framework (we should already have the driver for this
in place)
- for the HDMI PHY registers: on Meson8/8b/8m2 (those were 32-bit SoCs
in case you're not familiar with them, they predate GXBB/GXL/...) I
wrote a PHY driver (which is already upstream:
drivers/phy/amlogic/phy-meson8-hdmi-tx.c) as that made most sense to
me

Then there's meson_venc.c which has two writes to HHI_GCLK_MPEG2.
I think those should go through CCF instead of directly accessing this register.

Also there's the VDAC registers in meson_encoder_cvbs.c:
I think Neil suggested at one point to make it a PHY driver. I even
started working on this (if you're curious: see [0] and [1]).
DT ABI backwards compatibility is also a concern here.

And finally there's the video clock tree programming in meson_vclk.c.
My understanding here is that video PLL settings are very sensitive
and require fine-tuning according to the desired output clock.
Since it's a bunch of clocks I'd say that direct programming of the
clock registers should be avoided and we need to go through CCF as
well.
But to me those register values are all magic (as I am not aware of
any documentation that's available to me which describes how to
determine the correct PLL register values - otherside the standard
en/m/n/frac/lock and reset bits).

I'm not saying that all of my thoughts are correct and immediately
need to be put into code.
Think of them more as an explanation to Jerome's reaction.

I think what we need next is a discussion on how to move forward with
device-tree ABI for new SoCs.
Neil, Jerome: I'd like to hear your feedback on this.

> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>   requiring modifications to the driver to handle this new access method.
This info should go into patch 1/11 to explain why the g12a compatible
string cannot be used as fallback.


Best regards,
Martin


[0] https://github.com/xdarklight/linux/commit/36e698edc25dc698a0d57b729a7a4587fafc0987
[1] https://github.com/xdarklight/linux/commit/824b792fdbd2d3c0b71b21e1105eca0aaad8daa6

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Jerome Brunet]

On Sun 12 Jan 2025 at 23:44, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> Hello,
>
> On Fri, Jan 10, 2025 at 6:39 AM Ao Xu via B4 Relay
> <devnull+ao.xu.amlogic.com@kernel.org> wrote:
>>
>> This patch series adds DRM support for the Amlogic S4-series SoCs.
>> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
> Thanks for your patches. With this mail I'll try to summarize my
> understanding of the situation with the drm/meson driver as I'm not
> sure how familiar you are with previous discussions.
>
>> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>>   As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
> Jerome has already commented on patch 3/11 that this mixes in too many
> IP blocks into one driver.
> This is not a new situation, the existing code is doing exactly the same.
>
> Jerome has previously sent a series which started "an effort to remove
> the use HHI syscon" [0] from the drm/meson hdmi driver.
> In the same mail he further notes: "[the patchset] stops short of
> making any controversial DT changes. To decouple the HDMI
> phy driver and main DRM driver, allowing the PHY to get hold of its
> registers, I believe a DT ABI break is inevitable. Ideally the
> register region of the PHY within the HHI should provided, not the
> whole HHI. That's pain for another day ..."
>
> For now I'm assuming you're familiar with device-tree ABI.
> If not then please let us know so we can elaborate further on this.
>
> My own notes for meson_dw_hdmi.c are:
> - we should not program HHI_HDMI_CLK_CNTL directly but go through CCF
> (common clock framework) instead (we should already have the driver
> for this in place)
> - we should not program HHI_MEM_PD_REG0 directly but go through the
> genpd/pmdomain framework (we should already have the driver for this
> in place)
> - for the HDMI PHY registers: on Meson8/8b/8m2 (those were 32-bit SoCs
> in case you're not familiar with them, they predate GXBB/GXL/...) I
> wrote a PHY driver (which is already upstream:
> drivers/phy/amlogic/phy-meson8-hdmi-tx.c) as that made most sense to
> me
>
> Then there's meson_venc.c which has two writes to HHI_GCLK_MPEG2.
> I think those should go through CCF instead of directly accessing this register.
>
> Also there's the VDAC registers in meson_encoder_cvbs.c:
> I think Neil suggested at one point to make it a PHY driver. I even
> started working on this (if you're curious: see [0] and [1]).
> DT ABI backwards compatibility is also a concern here.
>
> And finally there's the video clock tree programming in meson_vclk.c.
> My understanding here is that video PLL settings are very sensitive
> and require fine-tuning according to the desired output clock.
> Since it's a bunch of clocks I'd say that direct programming of the
> clock registers should be avoided and we need to go through CCF as
> well.
> But to me those register values are all magic (as I am not aware of
> any documentation that's available to me which describes how to
> determine the correct PLL register values - otherside the standard
> en/m/n/frac/lock and reset bits).
>
> I'm not saying that all of my thoughts are correct and immediately
> need to be put into code.
> Think of them more as an explanation to Jerome's reaction.
>
> I think what we need next is a discussion on how to move forward with
> device-tree ABI for new SoCs.
> Neil, Jerome: I'd like to hear your feedback on this.

I completely agree with your description of the problem, that and
Krzysztof's remark on patch 6. This is not new with this series indeed,
so it does not introduce new problems really but it compounds the
existing ones.

Addressing those issues, if we want to, will get more difficult as more
support is added for sure.

>
>> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>>   requiring modifications to the driver to handle this new access method.

Regmap buses are made for those cases where the registers are the same,
but accessed differently. There is an example in the patchset referenced by
Martin, to handle GXL and G12 diff.

> This info should go into patch 1/11 to explain why the g12a compatible
> string cannot be used as fallback.
>
>
> Best regards,
> Martin
>
>
> [0] https://github.com/xdarklight/linux/commit/36e698edc25dc698a0d57b729a7a4587fafc0987
> [1] https://github.com/xdarklight/linux/commit/824b792fdbd2d3c0b71b21e1105eca0aaad8daa6

-- 
Jerome

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Ao Xu]

在 2025/1/15 1:50, Jerome Brunet 写道:
> [ EXTERNAL EMAIL ]
>
> On Sun 12 Jan 2025 at 23:44, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
>> Hello,
>>
>> On Fri, Jan 10, 2025 at 6:39 AM Ao Xu via B4 Relay
>> <devnull+ao.xu.amlogic.com@kernel.org> wrote:
>>> This patch series adds DRM support for the Amlogic S4-series SoCs.
>>> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
>> Thanks for your patches. With this mail I'll try to summarize my
>> understanding of the situation with the drm/meson driver as I'm not
>> sure how familiar you are with previous discussions.
>>
>>> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>>>    As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
>> Jerome has already commented on patch 3/11 that this mixes in too many
>> IP blocks into one driver.
>> This is not a new situation, the existing code is doing exactly the same.
>>
>> Jerome has previously sent a series which started "an effort to remove
>> the use HHI syscon" [0] from the drm/meson hdmi driver.
>> In the same mail he further notes: "[the patchset] stops short of
>> making any controversial DT changes. To decouple the HDMI
>> phy driver and main DRM driver, allowing the PHY to get hold of its
>> registers, I believe a DT ABI break is inevitable. Ideally the
>> register region of the PHY within the HHI should provided, not the
>> whole HHI. That's pain for another day ..."
>>
>> For now I'm assuming you're familiar with device-tree ABI.
>> If not then please let us know so we can elaborate further on this.
>>
>> My own notes for meson_dw_hdmi.c are:
>> - we should not program HHI_HDMI_CLK_CNTL directly but go through CCF
>> (common clock framework) instead (we should already have the driver
>> for this in place)
>> - we should not program HHI_MEM_PD_REG0 directly but go through the
>> genpd/pmdomain framework (we should already have the driver for this
>> in place)
>> - for the HDMI PHY registers: on Meson8/8b/8m2 (those were 32-bit SoCs
>> in case you're not familiar with them, they predate GXBB/GXL/...) I
>> wrote a PHY driver (which is already upstream:
>> drivers/phy/amlogic/phy-meson8-hdmi-tx.c) as that made most sense to
>> me
>>
>> Then there's meson_venc.c which has two writes to HHI_GCLK_MPEG2.
>> I think those should go through CCF instead of directly accessing this register.
>>
>> Also there's the VDAC registers in meson_encoder_cvbs.c:
>> I think Neil suggested at one point to make it a PHY driver. I even
>> started working on this (if you're curious: see [0] and [1]).
>> DT ABI backwards compatibility is also a concern here.
>>
>> And finally there's the video clock tree programming in meson_vclk.c.
>> My understanding here is that video PLL settings are very sensitive
>> and require fine-tuning according to the desired output clock.
>> Since it's a bunch of clocks I'd say that direct programming of the
>> clock registers should be avoided and we need to go through CCF as
>> well.
>> But to me those register values are all magic (as I am not aware of
>> any documentation that's available to me which describes how to
>> determine the correct PLL register values - otherside the standard
>> en/m/n/frac/lock and reset bits).
>>
>> I'm not saying that all of my thoughts are correct and immediately
>> need to be put into code.
>> Think of them more as an explanation to Jerome's reaction.
>>
>> I think what we need next is a discussion on how to move forward with
>> device-tree ABI for new SoCs.
>> Neil, Jerome: I'd like to hear your feedback on this.
> I completely agree with your description of the problem, that and
> Krzysztof's remark on patch 6. This is not new with this series indeed,
> so it does not introduce new problems really but it compounds the
> existing ones.
>
> Addressing those issues, if we want to, will get more difficult as more
> support is added for sure.

Hi, Jerome, Neil, Martin

     Thanks for your review. I hadn't noticed Jerome's patchsets before, 
and he has already done some excellent work.

     Indeed, the current code is overly coupled, with HHI and VPU regmap 
mixed together. It also contains a lot of redundant code, which is not 
very conducive to extension and maintenance.

     We are also considering ways to improve the DRM Meson code, and 
this is a good attempt.

     The code should reuse frameworks like CCF, reset, PHY, and PD as 
much as possible.

     I'm more than happy to collaborate on restructuring theAmlogic DRM 
driver to make it better!

>>> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>>>    requiring modifications to the driver to handle this new access method.
> Regmap buses are made for those cases where the registers are the same,
> but accessed differently. There is an example in the patchset referenced by
> Martin, to handle GXL and G12 diff.
>
>> This info should go into patch 1/11 to explain why the g12a compatible
>> string cannot be used as fallback.
>>
>>
>> Best regards,
>> Martin
>>
>>
>> [0] https://github.com/xdarklight/linux/commit/36e698edc25dc698a0d57b729a7a4587fafc0987
>> [1] https://github.com/xdarklight/linux/commit/824b792fdbd2d3c0b71b21e1105eca0aaad8daa6
> --
> Jerome

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Ao Xu]

On 2025/1/15 1:50, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Sun 12 Jan 2025 at 23:44, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
>> Hello,
>>
>> On Fri, Jan 10, 2025 at 6:39 AM Ao Xu via B4 Relay
>> <devnull+ao.xu.amlogic.com@kernel.org> wrote:
>>> This patch series adds DRM support for the Amlogic S4-series SoCs.
>>> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
>> Thanks for your patches. With this mail I'll try to summarize my
>> understanding of the situation with the drm/meson driver as I'm not
>> sure how familiar you are with previous discussions.
>>
>>> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>>>    As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
>> Jerome has already commented on patch 3/11 that this mixes in too many
>> IP blocks into one driver.
>> This is not a new situation, the existing code is doing exactly the same.
>>
>> Jerome has previously sent a series which started "an effort to remove
>> the use HHI syscon" [0] from the drm/meson hdmi driver.
>> In the same mail he further notes: "[the patchset] stops short of
>> making any controversial DT changes. To decouple the HDMI
>> phy driver and main DRM driver, allowing the PHY to get hold of its
>> registers, I believe a DT ABI break is inevitable. Ideally the
>> register region of the PHY within the HHI should provided, not the
>> whole HHI. That's pain for another day ..."
>>
>> For now I'm assuming you're familiar with device-tree ABI.
>> If not then please let us know so we can elaborate further on this.
>>
>> My own notes for meson_dw_hdmi.c are:
>> - we should not program HHI_HDMI_CLK_CNTL directly but go through CCF
>> (common clock framework) instead (we should already have the driver
>> for this in place)
>> - we should not program HHI_MEM_PD_REG0 directly but go through the
>> genpd/pmdomain framework (we should already have the driver for this
>> in place)
>> - for the HDMI PHY registers: on Meson8/8b/8m2 (those were 32-bit SoCs
>> in case you're not familiar with them, they predate GXBB/GXL/...) I
>> wrote a PHY driver (which is already upstream:
>> drivers/phy/amlogic/phy-meson8-hdmi-tx.c) as that made most sense to
>> me
>>
>> Then there's meson_venc.c which has two writes to HHI_GCLK_MPEG2.
>> I think those should go through CCF instead of directly accessing this register.
>>
>> Also there's the VDAC registers in meson_encoder_cvbs.c:
>> I think Neil suggested at one point to make it a PHY driver. I even
>> started working on this (if you're curious: see [0] and [1]).
>> DT ABI backwards compatibility is also a concern here.
>>
>> And finally there's the video clock tree programming in meson_vclk.c.
>> My understanding here is that video PLL settings are very sensitive
>> and require fine-tuning according to the desired output clock.
>> Since it's a bunch of clocks I'd say that direct programming of the
>> clock registers should be avoided and we need to go through CCF as
>> well.
>> But to me those register values are all magic (as I am not aware of
>> any documentation that's available to me which describes how to
>> determine the correct PLL register values - otherside the standard
>> en/m/n/frac/lock and reset bits).
>>
>> I'm not saying that all of my thoughts are correct and immediately
>> need to be put into code.
>> Think of them more as an explanation to Jerome's reaction.
>>
>> I think what we need next is a discussion on how to move forward with
>> device-tree ABI for new SoCs.
>> Neil, Jerome: I'd like to hear your feedback on this.
> I completely agree with your description of the problem, that and
> Krzysztof's remark on patch 6. This is not new with this series indeed,
> so it does not introduce new problems really but it compounds the
> existing ones.
>
> Addressing those issues, if we want to, will get more difficult as more
> support is added for sure.

Hi，jerome

     What are the next steps for "an effort to remove the use HHI 
syscon" patch set, and what is the schedule?

>>> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>>>    requiring modifications to the driver to handle this new access method.
> Regmap buses are made for those cases where the registers are the same,
> but accessed differently. There is an example in the patchset referenced by
> Martin, to handle GXL and G12 diff.
>
>> This info should go into patch 1/11 to explain why the g12a compatible
>> string cannot be used as fallback.
>>
>>
>> Best regards,
>> Martin
>>
>>
>> [0] https://github.com/xdarklight/linux/commit/36e698edc25dc698a0d57b729a7a4587fafc0987
>> [1] https://github.com/xdarklight/linux/commit/824b792fdbd2d3c0b71b21e1105eca0aaad8daa6
> --
> Jerome

Re: [PATCH 00/11] Subject: [PATCH 00/11] Add DRM support for Amlogic S4

[Jerome Brunet]

On Wed 22 Jan 2025 at 17:50, Ao Xu <ao.xu@amlogic.com> wrote:

> On 2025/1/15 1:50, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Sun 12 Jan 2025 at 23:44, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>>
>>> Hello,
>>>
>>> On Fri, Jan 10, 2025 at 6:39 AM Ao Xu via B4 Relay
>>> <devnull+ao.xu.amlogic.com@kernel.org> wrote:
>>>> This patch series adds DRM support for the Amlogic S4-series SoCs.
>>>> Compared to the Amlogic G12-series, the S4-series introduces the following changes:
>>> Thanks for your patches. With this mail I'll try to summarize my
>>> understanding of the situation with the drm/meson driver as I'm not
>>> sure how familiar you are with previous discussions.
>>>
>>>> 1 The S4-series splits the HIU into three separate components: `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
>>>>    As a result, VENC and VCLK drivers are updated with S4-specific compatible strings to accommodate these changes.
>>> Jerome has already commented on patch 3/11 that this mixes in too many
>>> IP blocks into one driver.
>>> This is not a new situation, the existing code is doing exactly the same.
>>>
>>> Jerome has previously sent a series which started "an effort to remove
>>> the use HHI syscon" [0] from the drm/meson hdmi driver.
>>> In the same mail he further notes: "[the patchset] stops short of
>>> making any controversial DT changes. To decouple the HDMI
>>> phy driver and main DRM driver, allowing the PHY to get hold of its
>>> registers, I believe a DT ABI break is inevitable. Ideally the
>>> register region of the PHY within the HHI should provided, not the
>>> whole HHI. That's pain for another day ..."
>>>
>>> For now I'm assuming you're familiar with device-tree ABI.
>>> If not then please let us know so we can elaborate further on this.
>>>
>>> My own notes for meson_dw_hdmi.c are:
>>> - we should not program HHI_HDMI_CLK_CNTL directly but go through CCF
>>> (common clock framework) instead (we should already have the driver
>>> for this in place)
>>> - we should not program HHI_MEM_PD_REG0 directly but go through the
>>> genpd/pmdomain framework (we should already have the driver for this
>>> in place)
>>> - for the HDMI PHY registers: on Meson8/8b/8m2 (those were 32-bit SoCs
>>> in case you're not familiar with them, they predate GXBB/GXL/...) I
>>> wrote a PHY driver (which is already upstream:
>>> drivers/phy/amlogic/phy-meson8-hdmi-tx.c) as that made most sense to
>>> me
>>>
>>> Then there's meson_venc.c which has two writes to HHI_GCLK_MPEG2.
>>> I think those should go through CCF instead of directly accessing this register.
>>>
>>> Also there's the VDAC registers in meson_encoder_cvbs.c:
>>> I think Neil suggested at one point to make it a PHY driver. I even
>>> started working on this (if you're curious: see [0] and [1]).
>>> DT ABI backwards compatibility is also a concern here.
>>>
>>> And finally there's the video clock tree programming in meson_vclk.c.
>>> My understanding here is that video PLL settings are very sensitive
>>> and require fine-tuning according to the desired output clock.
>>> Since it's a bunch of clocks I'd say that direct programming of the
>>> clock registers should be avoided and we need to go through CCF as
>>> well.
>>> But to me those register values are all magic (as I am not aware of
>>> any documentation that's available to me which describes how to
>>> determine the correct PLL register values - otherside the standard
>>> en/m/n/frac/lock and reset bits).
>>>
>>> I'm not saying that all of my thoughts are correct and immediately
>>> need to be put into code.
>>> Think of them more as an explanation to Jerome's reaction.
>>>
>>> I think what we need next is a discussion on how to move forward with
>>> device-tree ABI for new SoCs.
>>> Neil, Jerome: I'd like to hear your feedback on this.
>> I completely agree with your description of the problem, that and
>> Krzysztof's remark on patch 6. This is not new with this series indeed,
>> so it does not introduce new problems really but it compounds the
>> existing ones.
>>
>> Addressing those issues, if we want to, will get more difficult as more
>> support is added for sure.
>
> Hi，jerome
>
>     What are the next steps for "an effort to remove the use HHI syscon"
> patch set, and what is the schedule?

I have no idea. You should check with Neil whether or not it is something he
wants to do and how.

If you (or anyone else) want to make a v2 out of the first clean-up I've
made [2], you are welcome to. I'm handling other things ATM and I don't
expect to get to it any time soon.

[2]: https://lore.kernel.org/linux-amlogic/20240730125023.710237-1-jbrunet@baylibre.com/

>
>>>> 2 The S4-series secures access to HDMITX DWC and TOP registers,
>>>>    requiring modifications to the driver to handle this new access method.
>> Regmap buses are made for those cases where the registers are the same,
>> but accessed differently. There is an example in the patchset referenced by
>> Martin, to handle GXL and G12 diff.
>>
>>> This info should go into patch 1/11 to explain why the g12a compatible
>>> string cannot be used as fallback.
>>>
>>>
>>> Best regards,
>>> Martin
>>>
>>>
>>> [0] https://github.com/xdarklight/linux/commit/36e698edc25dc698a0d57b729a7a4587fafc0987
>>> [1]
>>> https://github.com/xdarklight/linux/commit/824b792fdbd2d3c0b71b21e1105eca0aaad8daa6
>> --
>> Jerome

-- 
Jerome