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Tue, 24 Dec 2019 08:30:11 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 58673C4479C; Tue, 24 Dec 2019 08:30:11 +0000 (UTC) Received: from [10.204.79.159] (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sramana) by smtp.codeaurora.org (Postfix) with ESMTPSA id 65DB0C43383; Tue, 24 Dec 2019 08:30:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 65DB0C43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sramana@codeaurora.org Subject: Re: [PATCH] arm64: Set SSBS for user threads while creation To: Anshuman Khandual , will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, will.deacon@arm.com References: <1577106146-8999-1-git-send-email-sramana@codeaurora.org> From: Srinivas Ramana Message-ID: <3a50c921-b37b-ea3d-1b9e-87113d3d3fd3@codeaurora.org> Date: Tue, 24 Dec 2019 14:00:05 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191224_003020_026552_45395967 X-CRM114-Status: GOOD ( 18.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/24/2019 12:36 PM, Anshuman Khandual wrote: > > > On 12/23/2019 06:32 PM, Srinivas Ramana wrote: >> Current SSBS implementation takes care of setting the >> SSBS bit in start_thread() for user threads. While this works >> for tasks launched with fork/clone followed by execve, for cases >> where userspace would just call fork (eg, Java applications) this >> leaves the SSBS bit unset. This results in performance >> regression for such tasks. >> >> It is understood that commit cbdf8a189a66 ("arm64: Force SSBS >> on context switch") masks this issue, but that was done for a >> different reason where heterogeneous CPUs(both SSBS supported >> and unsupported) are present. It is appropriate to take care >> of the SSBS bit for all threads while creation itself. > > So this fixes the situation (i.e low performance) from the creation time > of a task with fork() which will never see a subsequent execve, till it > gets context switched for the very first time ? > Yes, that is correct. >> >> Fixes: 8f04e8e6e29c ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3") >> Signed-off-by: Srinivas Ramana >> --- >> arch/arm64/kernel/process.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >> index 71f788cd2b18..a8f05cc39261 100644 >> --- a/arch/arm64/kernel/process.c >> +++ b/arch/arm64/kernel/process.c >> @@ -399,6 +399,13 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, >> */ >> if (clone_flags & CLONE_SETTLS) >> p->thread.uw.tp_value = childregs->regs[3]; >> + >> + if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) { >> + if (is_compat_thread(task_thread_info(p))) >> + set_compat_ssbs_bit(childregs); >> + else >> + set_ssbs_bit(childregs); >> + } >> } else { >> memset(childregs, 0, sizeof(struct pt_regs)); >> childregs->pstate = PSR_MODE_EL1h; >> Thanks, -- Srinivas R -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel