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([2001:8003:e5b0:9f00:dbbc:1945:6e65:ec5]) by smtp.gmail.com with ESMTPSA id c24-20020a170902b69800b001bb1f0605b2sm237330pls.214.2023.09.20.20.27.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Sep 2023 20:27:43 -0700 (PDT) Message-ID: <3a592951-5dda-258d-56fc-ddb11a00fdf1@redhat.com> Date: Thu, 21 Sep 2023 13:27:37 +1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 1/2] arm64: tlbflush: Rename MAX_TLBI_OPS To: Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , Will Deacon , Catalin Marinas , linux-arm-kernel@lists.infradead.org References: <20230920080133.944717-1-oliver.upton@linux.dev> <20230920080133.944717-2-oliver.upton@linux.dev> From: Gavin Shan In-Reply-To: <20230920080133.944717-2-oliver.upton@linux.dev> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_202749_964741_D0B70B19 X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/20/23 18:01, Oliver Upton wrote: > Perhaps unsurprisingly, I-cache invalidations suffer from performance > issues similar to TLB invalidations on certain systems. TLB and I-cache > maintenance all result in DVM on the mesh, which is where the real > bottleneck lies. > > Rename the heuristic to point the finger at DVM, such that it may be > reused for limiting I-cache invalidations. > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/tlbflush.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > Reviewed-by: Gavin Shan Tested-by: Gavin Shan > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index b149cf9f91bc..3431d37e5054 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -333,7 +333,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) > * This is meant to avoid soft lock-ups on large TLB flushing ranges and not > * necessarily a performance improvement. > */ > -#define MAX_TLBI_OPS PTRS_PER_PTE > +#define MAX_DVM_OPS PTRS_PER_PTE > > /* > * __flush_tlb_range_op - Perform TLBI operation upon a range > @@ -413,12 +413,12 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, > > /* > * When not uses TLB range ops, we can handle up to > - * (MAX_TLBI_OPS - 1) pages; > + * (MAX_DVM_OPS - 1) pages; > * When uses TLB range ops, we can handle up to > * (MAX_TLBI_RANGE_PAGES - 1) pages. > */ > if ((!system_supports_tlb_range() && > - (end - start) >= (MAX_TLBI_OPS * stride)) || > + (end - start) >= (MAX_DVM_OPS * stride)) || > pages >= MAX_TLBI_RANGE_PAGES) { > flush_tlb_mm(vma->vm_mm); > return; > @@ -451,7 +451,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end > { > unsigned long addr; > > - if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) { > + if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) { > flush_tlb_all(); > return; > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel