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Fri, 14 Aug 2026 04:05:51 -0700 (PDT) X-Received: by 2002:aa7:8681:0:b0:850:a86b:6ce1 with SMTP id d2e1a72fcca58-850a86b8ac4mr1694141b3a.0.1786705550748; Fri, 14 Aug 2026 04:05:50 -0700 (PDT) Received: from [10.92.210.190] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8517d01f300sm312585b3a.18.2026.08.14.04.05.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Aug 2026 04:05:50 -0700 (PDT) Message-ID: <3d8101b2-558b-48e0-badd-a8e439c74dd0@oss.qualcomm.com> Date: Fri, 14 Aug 2026 16:35:43 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] dt-bindings: arm: ras: Introduce bindings for ARM RAS error sources To: Krzysztof Kozlowski , Trilok Soni Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Ruidong Tian , Tony Luck , Borislav Petkov , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, faruque.ansari@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com References: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> <20260720081954.1858180-2-umang.chheda@oss.qualcomm.com> <20260728-determined-lorikeet-from-tartarus-cf124e@quoll> Content-Language: en-US From: Umang Chheda In-Reply-To: <20260728-determined-lorikeet-from-tartarus-cf124e@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE0MDA4MyBTYWx0ZWRfX1T2PFIzyNH8V gk8mo51Q1/mKOE0W4cJ9zYC0f67mkw4ezFZotV64fV5FdAq40i6ndLIAs9vdtks6DoLKSc8EtXM OrQZS1VNH2v6dJ1cilIC6memu50H9wSf98n73KZ+juvCcMnMBVIzHOB1gsUCjrBJCaJDUXXuF0q 3pXZvFf3go7XTHA2/0iQWSfVrZNz4pI2nWURLFiLH9jEMIxm4NScX42m4PZKkxTyIQUN5H5rYv8 XmQ4zbf+mf2hT2aABip9x+yCWLJR4U7b0qv4LenA+cD7xT6ohTEkVCAsEY02UwZCMZ6i6tqVrnl oSsude8WLzMmeL0KnCaJ455J9O3TXquFSzyxnEqWp5Vqs0Hk++8UZMXbml4R21dbIvyy8MHyxlH /a8hE9W+5uUEFXNfRhWPRGaDOF9hlvupveA2B5sSjLAa7zYfH8VnqlDF0TVEaFtLb2ZMnudiQJc xFxLu3bB8t2Wo1uiI2w== X-Proofpoint-GUID: ystUVexvzsKIPRIYlLRwH70wQQ27Kwqu X-Proofpoint-ORIG-GUID: ystUVexvzsKIPRIYlLRwH70wQQ27Kwqu X-Proofpoint-Spam-Info: AW1haW4tMjYwODE0MDA4MyBTYWx0ZWRfX9gcVnUU6Ujd+ gzpfhZ3Je29wKv3snaaNh1MfoR+LSYW/QGOKBYUO7x8IsAoYEvpbx5fQ6l3jRKDz2pG+ccW4n4/ bqVK+PUZ8ArS511DVCj0JM6K6FiU88s= X-Authority-Analysis: v=2.4 cv=cMTQdFeN c=1 sm=1 tr=0 ts=6a7ef690 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=3LPT6PZN0yckniG3iNgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-14_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608140083 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260814_040553_216652_7BAB799D X-CRM114-Status: GOOD ( 20.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Krzysztof, Trilok, On 7/28/2026 2:17 PM, Krzysztof Kozlowski wrote: > On Mon, Jul 27, 2026 at 01:51:08PM -0700, Trilok Soni wrote: >> On 7/20/2026 1:19 AM, Umang Chheda wrote: >>> new file mode 100644 >>> index 000000000000..c2f4e1f8243e >>> --- /dev/null >>> +++ b/include/dt-bindings/arm/arm-ras.h >>> @@ -0,0 +1,11 @@ >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >>> + >>> +#ifndef _DT_BINDINGS_ARM_RAS_H >>> +#define _DT_BINDINGS_ARM_RAS_H >>> + >>> +/* arm,group-format - error record group register window page size */ >>> +#define ARM_RAS_GROUP_4K 0 /* 4 KiB, 1 ERRGSR */ >>> +#define ARM_RAS_GROUP_16K 1 /* 16 KiB, 4 ERRGSRs */ >>> +#define ARM_RAS_GROUP_64K 2 /* 64 KiB, 14 ERRGSRs */ >> >> Do you want me to have different DT for 4k and 16k and 64k? This is not a right approach. >> > > Is this page size or register window page size? If the latter, why would > device registers be a binding? Thanks for the review. To clarify both points: On "page size" vs "register window page size": The comment in arm-ras.h is misleading — I will fix it. It is neither a memory page size nor a kernel page granularity. The 4K/16K/64K values refer to the three fixed error record group register window layouts defined by the ARM RAS architecture specification. The naming comes from the ARM spec itself which uses these sizes to describe the three possible layouts of the MMIO window. I will update the comment to make this clear. On "why would device registers be a binding": This is a static hardware property — it describes which of the three fixed register layouts the hardware block implements, and it is not self-discoverable at runtime. There is no register within the window that encodes the layout. The driver needs it upfront to: - Determine the correct ioremap size - Know how many ERRGSR registers to scan - Know the array length for arm,record-impl and arm,status-reporting I will also fix the misleading comment in arm-ras.h from "register window page size" to "error record group register window layout" in v3. > > Best regards, > Krzysztof > Thanks, Umang