From: James Clark <james.clark@linaro.org>
To: Mike Leach <mike.leach@linaro.org>
Cc: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>,
kernel@oss.qualcomm.com, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Subject: Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR
Date: Thu, 14 Aug 2025 11:52:58 +0100 [thread overview]
Message-ID: <3da37a91-9512-405b-ba74-c1feb80b4dd2@linaro.org> (raw)
In-Reply-To: <CAJ9a7Vif9__iXasPWi0uUhXNJ63xQBtBksT17MvQ-+rDMVxuAQ@mail.gmail.com>
On 14/08/2025 11:25 am, Mike Leach wrote:
> On Thu, 14 Aug 2025 at 10:51, James Clark <james.clark@linaro.org> wrote:
>>
>>
>>
>> On 12/08/2025 9:24 am, Yuanfang Zhang wrote:
>>> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
>>> To avoid invalid accesses, introduce a check on numextinsel
>>> (derived from TRCIDR5[11:9]) before reading or writing to this register.
>>>
>>> Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses")
>>
>> This tag isn't right. Although this is where the register accesses were
>> last touched, the root issue was present from the introduction of the
>> driver.
>>
>
> Memory mapped access to unimplemented registers are RES0 so won't fail
> - the issue is the system register access where an undefined exception
> can be triggered.
>
> Mike
>
Ah, good point. I assumed that commit was just a refactor.
next prev parent reply other threads:[~2025-08-14 15:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 8:24 [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR Yuanfang Zhang
2025-08-12 9:30 ` James Clark
2025-08-14 9:30 ` Mike Leach
2025-08-14 9:51 ` James Clark
2025-08-14 10:25 ` Mike Leach
2025-08-14 10:52 ` James Clark [this message]
2025-09-02 9:07 ` Suzuki K Poulose
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