* [PATCH 0/3] irqchip: mstar: msc313 intc driver
@ 2020-08-05 11:00 Daniel Palmer
2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Daniel Palmer @ 2020-08-05 11:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, jason, arnd, maz, Daniel Palmer, linux-kernel,
robh+dt, tglx
This driver adds support for the interrupt controllers
present between the various IP blocks and the ARM GIC
in MStar/SigmaStar Armv7 SoCs.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code. Presumably because they can be FIQ
interrupts. Right now the FIQ bypass is disabled in the
GIC so they operate just the same as the IRQ interrupts.
The register layouts are the same for both. The FIQ one
needs to have the status bit cleared on EOI so that difference
is handled by a compatible string difference.
I initially made this an RFC because this is my first
interrupt controller driver and I expect to have made a
bunch of mistakes. I've cleaned this up a bit since then
but I still expect it's not 100% correct. Especially
the offset to map the INTC interrupt to the GIC interrupt.
Daniel Palmer (3):
dt: bindings: interrupt-controller: Add binding description for
msc313-intc
irqchip: mstar: msc313-intc interrupt controller driver
ARM: mstar: Add interrupt controller to base dtsi
.../mstar,msc313-intc.yaml | 79 +++++++
MAINTAINERS | 2 +
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++
5 files changed, 312 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml
create mode 100644 drivers/irqchip/irq-msc313-intc.c
--
2.27.0
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc 2020-08-05 11:00 [PATCH 0/3] irqchip: mstar: msc313 intc driver Daniel Palmer @ 2020-08-05 11:00 ` Daniel Palmer 2020-08-06 14:10 ` Rob Herring 2020-08-06 14:15 ` Rob Herring 2020-08-05 11:00 ` [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver Daniel Palmer 2020-08-05 11:00 ` [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Daniel Palmer 2 siblings, 2 replies; 10+ messages in thread From: Daniel Palmer @ 2020-08-05 11:00 UTC (permalink / raw) To: linux-arm-kernel Cc: devicetree, jason, arnd, maz, Daniel Palmer, linux-kernel, robh+dt, tglx Adds a YAML description of the binding for the msc313-intc. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- .../mstar,msc313-intc.yaml | 79 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml new file mode 100644 index 000000000000..e256887aa847 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/mstar,msc313-intc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar ARMv7 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + "#interrupt-cells": + const: 2 + + compatible: + enum: + - mstar,msc313-intc-irq + - mstar,msc313-intc-fiq + + reg: + maxItems: 1 + + interrupt-controller: true + + mstar,gic-offset: + description: + Offset added to the intc irq number to get the parent GIC irq. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 255 + + mstar,nr-interrupts: + description: + Number of interrupt lines this intc has. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + maximum: 64 + +required: + - "#interrupt-cells" + - compatible + - reg + - interrupt-controller + - mstar,gic-offset + - mstar,nr-interrupts + +additionalProperties: false + +examples: + - | + intc_fiq: intc@201310 { + compatible = "mstar,msc313-intc-fiq"; + interrupt-controller; + reg = <0x201310 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <96>; + mstar,nr-interrupts = <32>; + }; + + - | + intc_irq: intc@201350 { + compatible = "mstar,msc313-intc-irq"; + interrupt-controller; + reg = <0x201350 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <32>; + mstar,nr-interrupts = <64>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index c8e8232c65da..6e64d17aad7b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2152,6 +2152,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* +F: Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc 2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer @ 2020-08-06 14:10 ` Rob Herring 2020-08-06 14:15 ` Rob Herring 1 sibling, 0 replies; 10+ messages in thread From: Rob Herring @ 2020-08-06 14:10 UTC (permalink / raw) To: Daniel Palmer Cc: devicetree, jason, arnd, maz, linux-kernel, robh+dt, tglx, linux-arm-kernel On Wed, 05 Aug 2020 20:00:50 +0900, Daniel Palmer wrote: > Adds a YAML description of the binding for the msc313-intc. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > --- > .../mstar,msc313-intc.yaml | 79 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml > My bot found errors running 'make dt_binding_check' on your patch: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.example.dt.yaml: intc@201310: 'mstar,gic-offset', 'mstar,nr-interrupts' do not match any of the regexes: '^#.*', '^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*', '^(keypad|m25p|max8952|max8997|max8998|mpmc),.*', '^(pinctrl-single|#pinctrl-single|PowerPC),.*', '^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*', '^(simple-audio-card|simple-graph-card|st-plgpio|st-spics|ts),.*', '^GEFanuc,.*', '^ORCL,.*', '^SUNW,.*', '^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$', '^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$', '^abilis,.*', '^abracon,.*', '^acme,.*', '^actions,.*', '^active-semi,.*', '^ad,.*', '^adafruit,.*', '^adapteva,.*', '^adaptrum,.*', '^adh,.*', '^adi,.*', '^advantech,.*', '^aeroflexgaisler,.*', '^al,.*', '^allegro,.*', '^allo,.*', '^allwinner,.*', '^alphascale,.*', '^alps,.*', '^altr,.*', '^amarula,.*', '^amazon,.*', '^amcc,.*', '^amd,.*', '^amed iatech,.*', '^amlogic,.*', '^ampire,.*', '^ams,.*', '^amstaos,.*', '^analogix,.*', '^andestech,.*', '^anvo,.*', '^apm,.*', '^aptina,.*', '^arasan,.*', '^archermind,.*', '^arctic,.*', '^arcx,.*', '^aries,.*', '^arm,.*', '^armadeus,.*', '^arrow,.*', '^artesyn,.*', '^asahi-kasei,.*', '^asc,.*', '^aspeed,.*', '^asus,.*', '^atlas,.*', '^atmel,.*', '^auo,.*', '^auvidea,.*', '^avago,.*', '^avia,.*', '^avic,.*', '^avnet,.*', '^awinic,.*', '^axentia,.*', '^axis,.*', '^azoteq,.*', '^azw,.*', '^baikal,.*', '^bananapi,.*', '^beacon,.*', '^beagle,.*', '^bhf,.*', '^bitmain,.*', '^boe,.*', '^bosch,.*', '^boundary,.*', '^brcm,.*', '^broadmobi,.*', '^bticino,.*', '^buffalo,.*', '^bur,.*', '^calaosystems,.*', '^calxeda,.*', '^capella,.*', '^cascoda,.*', '^catalyst,.*', '^cavium,.*', '^cdns,.*', '^cdtech,.*', '^cellwise,.*', '^ceva,.*', '^checkpoint,.*', '^chipidea,.*', '^chipone,.*', '^chipspark,.*', '^chrontel,.*', '^chrp,.*', '^chunghwa,.*', '^chuwi,.*', '^ciaa,.*', '^cirrus,.*', '^cloudengines,.*' , '^cnm,.*', '^cnxt,.*', '^colorfly,.*', '^compulab,.*', '^coreriver,.*', '^corpro,.*', '^cortina,.*', '^cosmic,.*', '^crane,.*', '^creative,.*', '^crystalfontz,.*', '^csky,.*', '^csq,.*', '^cubietech,.*', '^cypress,.*', '^cznic,.*', '^dallas,.*', '^dataimage,.*', '^davicom,.*', '^dell,.*', '^delta,.*', '^denx,.*', '^devantech,.*', '^dh,.*', '^difrnce,.*', '^digi,.*', '^digilent,.*', '^dioo,.*', '^dlc,.*', '^dlg,.*', '^dlink,.*', '^dmo,.*', '^domintech,.*', '^dongwoon,.*', '^dptechnics,.*', '^dragino,.*', '^dserve,.*', '^dynaimage,.*', '^ea,.*', '^ebs-systart,.*', '^ebv,.*', '^eckelmann,.*', '^edt,.*', '^eeti,.*', '^einfochips,.*', '^elan,.*', '^elgin,.*', '^elida,.*', '^embest,.*', '^emlid,.*', '^emmicro,.*', '^empire-electronix,.*', '^emtrion,.*', '^endless,.*', '^ene,.*', '^energymicro,.*', '^engicam,.*', '^epcos,.*', '^epfl,.*', '^epson,.*', '^esp,.*', '^est,.*', '^ettus,.*', '^eukrea,.*', '^everest,.*', '^everspin,.*', '^evervision,.*', '^exar,.*', '^excito,.*', '^ezchip,.*', ' ^facebook,.*', '^fairphone,.*', '^faraday,.*', '^fastrax,.*', '^fcs,.*', '^feixin,.*', '^feiyang,.*', '^firefly,.*', '^focaltech,.*', '^frida,.*', '^friendlyarm,.*', '^fsl,.*', '^fujitsu,.*', '^gardena,.*', '^gateworks,.*', '^gcw,.*', '^ge,.*', '^geekbuying,.*', '^gef,.*', '^gemei,.*', '^geniatech,.*', '^giantec,.*', '^giantplus,.*', '^globalscale,.*', '^globaltop,.*', '^gmt,.*', '^goodix,.*', '^google,.*', '^grinn,.*', '^grmn,.*', '^gumstix,.*', '^gw,.*', '^hannstar,.*', '^haoyu,.*', '^hardkernel,.*', '^hideep,.*', '^himax,.*', '^hisilicon,.*', '^hit,.*', '^hitex,.*', '^holt,.*', '^holtek,.*', '^honeywell,.*', '^hoperun,.*', '^hp,.*', '^hsg,.*', '^hugsun,.*', '^hwacom,.*', '^hydis,.*', '^hyundai,.*', '^i2se,.*', '^ibm,.*', '^icplus,.*', '^idt,.*', '^ifi,.*', '^ilitek,.*', '^img,.*', '^incircuit,.*', '^inet-tek,.*', '^infineon,.*', '^inforce,.*', '^ingenic,.*', '^innolux,.*', '^inside-secure,.*', '^inspur,.*', '^intel,.*', '^intercontrol,.*', '^invensense,.*', '^inversepath,.*', '^i om,.*', '^isee,.*', '^isil,.*', '^issi,.*', '^ite,.*', '^itead,.*', '^ivo,.*', '^iwave,.*', '^jdi,.*', '^jedec,.*', '^jesurun,.*', '^jianda,.*', '^kam,.*', '^karo,.*', '^keithkoep,.*', '^keymile,.*', '^khadas,.*', '^kiebackpeter,.*', '^kinetic,.*', '^kingdisplay,.*', '^kingnovel,.*', '^kionix,.*', '^kobo,.*', '^koe,.*', '^kontron,.*', '^kosagi,.*', '^kyo,.*', '^lacie,.*', '^laird,.*', '^lamobo,.*', '^lantiq,.*', '^lattice,.*', '^leadtek,.*', '^leez,.*', '^lego,.*', '^lemaker,.*', '^lenovo,.*', '^lg,.*', '^lgphilips,.*', '^libretech,.*', '^licheepi,.*', '^linaro,.*', '^linksprite,.*', '^linksys,.*', '^linutronix,.*', '^linux,.*', '^linx,.*', '^lltc,.*', '^logicpd,.*', '^logictechno,.*', '^longcheer,.*', '^loongson,.*', '^lsi,.*', '^lwn,.*', '^lxa,.*', '^macnica,.*', '^mapleboard,.*', '^marvell,.*', '^maxbotix,.*', '^maxim,.*', '^mbvl,.*', '^mcube,.*', '^meas,.*', '^mecer,.*', '^mediatek,.*', '^megachips,.*', '^mele,.*', '^melexis,.*', '^melfas,.*', '^mellanox,.*', '^memsic,.*', '^men lo,.*', '^merrii,.*', '^micrel,.*', '^microchip,.*', '^microcrystal,.*', '^micron,.*', '^microsoft,.*', '^mikroe,.*', '^mikrotik,.*', '^miniand,.*', '^minix,.*', '^miramems,.*', '^mitsubishi,.*', '^mosaixtech,.*', '^motorola,.*', '^moxa,.*', '^mpl,.*', '^mps,.*', '^mqmaker,.*', '^mrvl,.*', '^mscc,.*', '^msi,.*', '^mti,.*', '^multi-inno,.*', '^mundoreader,.*', '^murata,.*', '^mxicy,.*', '^myir,.*', '^national,.*', '^nec,.*', '^neonode,.*', '^netgear,.*', '^netlogic,.*', '^netron-dy,.*', '^netxeon,.*', '^neweast,.*', '^newhaven,.*', '^nexbox,.*', '^nextthing,.*', '^ni,.*', '^nintendo,.*', '^nlt,.*', '^nokia,.*', '^nordic,.*', '^novtech,.*', '^nutsboard,.*', '^nuvoton,.*', '^nvd,.*', '^nvidia,.*', '^nxp,.*', '^oceanic,.*', '^okaya,.*', '^oki,.*', '^olimex,.*', '^olpc,.*', '^onion,.*', '^onnn,.*', '^ontat,.*', '^opalkelly,.*', '^opencores,.*', '^openrisc,.*', '^option,.*', '^oranth,.*', '^orisetech,.*', '^ortustech,.*', '^osddisplays,.*', '^overkiz,.*', '^ovti,.*', '^oxsemi,.*', '^ozzma ker,.*', '^panasonic,.*', '^parade,.*', '^parallax,.*', '^pda,.*', '^pericom,.*', '^pervasive,.*', '^phicomm,.*', '^phytec,.*', '^picochip,.*', '^pine64,.*', '^pineriver,.*', '^pixcir,.*', '^plantower,.*', '^plathome,.*', '^plda,.*', '^plx,.*', '^pni,.*', '^pocketbook,.*', '^polaroid,.*', '^portwell,.*', '^poslab,.*', '^pov,.*', '^powervr,.*', '^primux,.*', '^probox2,.*', '^prt,.*', '^pulsedlight,.*', '^purism,.*', '^qca,.*', '^qcom,.*', '^qemu,.*', '^qi,.*', '^qiaodian,.*', '^qihua,.*', '^qnap,.*', '^radxa,.*', '^raidsonic,.*', '^ralink,.*', '^ramtron,.*', '^raspberrypi,.*', '^raydium,.*', '^rda,.*', '^realtek,.*', '^renesas,.*', '^rervision,.*', '^richtek,.*', '^ricoh,.*', '^rikomagic,.*', '^riscv,.*', '^rockchip,.*', '^rocktech,.*', '^rohm,.*', '^ronbo,.*', '^roofull,.*', '^samsung,.*', '^samtec,.*', '^sancloud,.*', '^sandisk,.*', '^satoz,.*', '^sbs,.*', '^schindler,.*', '^seagate,.*', '^seirobotics,.*', '^semtech,.*', '^sensirion,.*', '^sensortek,.*', '^sff,.*', '^sgd,.*', '^sgm icro,.*', '^sgx,.*', '^sharp,.*', '^shimafuji,.*', '^shiratech,.*', '^si-en,.*', '^si-linux,.*', '^sifive,.*', '^sigma,.*', '^sii,.*', '^sil,.*', '^silabs,.*', '^silead,.*', '^silergy,.*', '^silex-insight,.*', '^siliconmitus,.*', '^simtek,.*', '^sinlinx,.*', '^sinovoip,.*', '^sipeed,.*', '^sirf,.*', '^sis,.*', '^sitronix,.*', '^skyworks,.*', '^smartlabs,.*', '^smsc,.*', '^snps,.*', '^sochip,.*', '^socionext,.*', '^solidrun,.*', '^solomon,.*', '^sony,.*', '^spansion,.*', '^sprd,.*', '^sst,.*', '^st,.*', '^st-ericsson,.*', '^starry,.*', '^startek,.*', '^ste,.*', '^stericsson,.*', '^summit,.*', '^sunchip,.*', '^swir,.*', '^syna,.*', '^synology,.*', '^tbs,.*', '^tbs-biometrics,.*', '^tcg,.*', '^tcl,.*', '^technexion,.*', '^technologic,.*', '^techstar,.*', '^tempo,.*', '^terasic,.*', '^tfc,.*', '^thine,.*', '^ti,.*', '^tianma,.*', '^tlm,.*', '^tmt,.*', '^topeet,.*', '^toppoly,.*', '^topwise,.*', '^toradex,.*', '^toshiba,.*', '^toumaz,.*', '^tpk,.*', '^tplink,.*', '^tpo,.*', '^tq,.*', '^t ronfy,.*', '^tronsmart,.*', '^truly,.*', '^tsd,.*', '^tyan,.*', '^u-blox,.*', '^u-boot,.*', '^ubnt,.*', '^ucrobotics,.*', '^udoo,.*', '^ugoos,.*', '^uniwest,.*', '^upisemi,.*', '^urt,.*', '^usi,.*', '^utoo,.*', '^v3,.*', '^vaisala,.*', '^vamrs,.*', '^variscite,.*', '^via,.*', '^videostrong,.*', '^virtio,.*', '^vishay,.*', '^visionox,.*', '^vitesse,.*', '^vivante,.*', '^vocore,.*', '^voipac,.*', '^vot,.*', '^vxt,.*', '^waveshare,.*', '^wd,.*', '^we,.*', '^wetek,.*', '^wexler,.*', '^whwave,.*', '^wi2wi,.*', '^winbond,.*', '^winstar,.*', '^wits,.*', '^wlf,.*', '^wm,.*', '^wobo,.*', '^x-powers,.*', '^xes,.*', '^xiaomi,.*', '^xillybus,.*', '^xinpeng,.*', '^xlnx,.*', '^xnano,.*', '^xunlong,.*', '^xylon,.*', '^yna,.*', '^yones-toptech,.*', '^ysoft,.*', '^zarlink,.*', '^zeitec,.*', '^zidoo,.*', '^zii,.*', '^zte,.*', '^zyxel,.*' /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.example.dt.yaml: intc@201310: $nodename:0: 'intc@201310' does not match '^interrupt-controller(@[0-9a-f,]+)*$' /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.example.dt.yaml: intc@201350: 'mstar,gic-offset', 'mstar,nr-interrupts' do not match any of the regexes: '^#.*', '^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*', '^(keypad|m25p|max8952|max8997|max8998|mpmc),.*', '^(pinctrl-single|#pinctrl-single|PowerPC),.*', '^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*', '^(simple-audio-card|simple-graph-card|st-plgpio|st-spics|ts),.*', '^GEFanuc,.*', '^ORCL,.*', '^SUNW,.*', '^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$', '^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$', '^abilis,.*', '^abracon,.*', '^acme,.*', '^actions,.*', '^active-semi,.*', '^ad,.*', '^adafruit,.*', '^adapteva,.*', '^adaptrum,.*', '^adh,.*', '^adi,.*', '^advantech,.*', '^aeroflexgaisler,.*', '^al,.*', '^allegro,.*', '^allo,.*', '^allwinner,.*', '^alphascale,.*', '^alps,.*', '^altr,.*', '^amarula,.*', '^amazon,.*', '^amcc,.*', '^amd,.*', '^amed iatech,.*', '^amlogic,.*', '^ampire,.*', '^ams,.*', '^amstaos,.*', '^analogix,.*', '^andestech,.*', '^anvo,.*', '^apm,.*', '^aptina,.*', '^arasan,.*', '^archermind,.*', '^arctic,.*', '^arcx,.*', '^aries,.*', '^arm,.*', '^armadeus,.*', '^arrow,.*', '^artesyn,.*', '^asahi-kasei,.*', '^asc,.*', '^aspeed,.*', '^asus,.*', '^atlas,.*', '^atmel,.*', '^auo,.*', '^auvidea,.*', '^avago,.*', '^avia,.*', '^avic,.*', '^avnet,.*', '^awinic,.*', '^axentia,.*', '^axis,.*', '^azoteq,.*', '^azw,.*', '^baikal,.*', '^bananapi,.*', '^beacon,.*', '^beagle,.*', '^bhf,.*', '^bitmain,.*', '^boe,.*', '^bosch,.*', '^boundary,.*', '^brcm,.*', '^broadmobi,.*', '^bticino,.*', '^buffalo,.*', '^bur,.*', '^calaosystems,.*', '^calxeda,.*', '^capella,.*', '^cascoda,.*', '^catalyst,.*', '^cavium,.*', '^cdns,.*', '^cdtech,.*', '^cellwise,.*', '^ceva,.*', '^checkpoint,.*', '^chipidea,.*', '^chipone,.*', '^chipspark,.*', '^chrontel,.*', '^chrp,.*', '^chunghwa,.*', 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'^toshiba,.*', '^toumaz,.*', '^tpk,.*', '^tplink,.*', '^tpo,.*', '^tq,.*', '^t ronfy,.*', '^tronsmart,.*', '^truly,.*', '^tsd,.*', '^tyan,.*', '^u-blox,.*', '^u-boot,.*', '^ubnt,.*', '^ucrobotics,.*', '^udoo,.*', '^ugoos,.*', '^uniwest,.*', '^upisemi,.*', '^urt,.*', '^usi,.*', '^utoo,.*', '^v3,.*', '^vaisala,.*', '^vamrs,.*', '^variscite,.*', '^via,.*', '^videostrong,.*', '^virtio,.*', '^vishay,.*', '^visionox,.*', '^vitesse,.*', '^vivante,.*', '^vocore,.*', '^voipac,.*', '^vot,.*', '^vxt,.*', '^waveshare,.*', '^wd,.*', '^we,.*', '^wetek,.*', '^wexler,.*', '^whwave,.*', '^wi2wi,.*', '^winbond,.*', '^winstar,.*', '^wits,.*', '^wlf,.*', '^wm,.*', '^wobo,.*', '^x-powers,.*', '^xes,.*', '^xiaomi,.*', '^xillybus,.*', '^xinpeng,.*', '^xlnx,.*', '^xnano,.*', '^xunlong,.*', '^xylon,.*', '^yna,.*', '^yones-toptech,.*', '^ysoft,.*', '^zarlink,.*', '^zeitec,.*', '^zidoo,.*', '^zii,.*', '^zte,.*', '^zyxel,.*' /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.example.dt.yaml: intc@201350: $nodename:0: 'intc@201350' does not match '^interrupt-controller(@[0-9a-f,]+)*$' See https://patchwork.ozlabs.org/patch/1341413 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc 2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer 2020-08-06 14:10 ` Rob Herring @ 2020-08-06 14:15 ` Rob Herring 2020-08-06 14:46 ` Daniel Palmer 1 sibling, 1 reply; 10+ messages in thread From: Rob Herring @ 2020-08-06 14:15 UTC (permalink / raw) To: Daniel Palmer Cc: devicetree, Jason Cooper, Arnd Bergmann, Marc Zyngier, linux-kernel@vger.kernel.org, Thomas Gleixner, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Wed, Aug 5, 2020 at 5:01 AM Daniel Palmer <daniel@0x0f.com> wrote: > > Adds a YAML description of the binding for the msc313-intc. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > --- > .../mstar,msc313-intc.yaml | 79 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml Why are you sending another version? You ignored the errors and my questions on the RFC. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc 2020-08-06 14:15 ` Rob Herring @ 2020-08-06 14:46 ` Daniel Palmer 0 siblings, 0 replies; 10+ messages in thread From: Daniel Palmer @ 2020-08-06 14:46 UTC (permalink / raw) To: Rob Herring Cc: DTML, Jason Cooper, Arnd Bergmann, Marc Zyngier, linux-kernel@vger.kernel.org, Thomas Gleixner, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Rob, On Thu, 6 Aug 2020 at 23:15, Rob Herring <robh+dt@kernel.org> wrote: > Why are you sending another version? You ignored the errors and my > questions on the RFC. Sorry I didn't think I got any responses RFC but after searching it looks like the email from your bot and your question about the two custom properties went into a folder I wasn't looking at. Based on Marc's feedback (that there should be an static irqchip struct for each variation) I'm going to drop the custom properties and make the metadata they had part of the driver. They were basically there to try to make the driver universal. Again sorry for my mishap. Daniel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver 2020-08-05 11:00 [PATCH 0/3] irqchip: mstar: msc313 intc driver Daniel Palmer 2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer @ 2020-08-05 11:00 ` Daniel Palmer 2020-08-05 16:26 ` Marc Zyngier 2020-08-05 11:00 ` [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Daniel Palmer 2 siblings, 1 reply; 10+ messages in thread From: Daniel Palmer @ 2020-08-05 11:00 UTC (permalink / raw) To: linux-arm-kernel Cc: devicetree, jason, arnd, maz, Daniel Palmer, linux-kernel, robh+dt, tglx, Willy Tarreau Add a driver for the two peripheral interrupt controllers in MStar MSC313 and other MStar/Sigmastar Armv7 SoCs. Supports both the "IRQ" and "FIQ" controllers that forward interrupts from the various IP blocks inside the SoC to the ARM GIC. They are basically the same thing except for one difference: The FIQ controller needs to clear the interrupt and the IRQ controller doesn't. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Tested-by: Willy Tarreau <w@1wt.eu> --- MAINTAINERS | 1 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 drivers/irqchip/irq-msc313-intc.c diff --git a/MAINTAINERS b/MAINTAINERS index 6e64d17aad7b..4d07403a7726 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2157,6 +2157,7 @@ F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ +F: drivers/irqchip/irq-msc313-intc.c ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky <mkpetch@internode.on.net> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 133f9c45744a..67f3ae3507b8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o +obj-$(CONFIG_ARCH_MSTARV7) += irq-msc313-intc.o diff --git a/drivers/irqchip/irq-msc313-intc.c b/drivers/irqchip/irq-msc313-intc.c new file mode 100644 index 000000000000..b50f5c858d38 --- /dev/null +++ b/drivers/irqchip/irq-msc313-intc.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Daniel Palmer + */ + +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#define REGOFF_MASK 0x0 +#define REGOFF_POLARITY 0x10 +#define REGOFF_STATUSCLEAR 0x20 +#define IRQSPERREG 16 +#define IRQBIT(hwirq) BIT((hwirq % IRQSPERREG)) +#define REGOFF(hwirq) ((hwirq >> 4) * 4) + +struct msc313_intc { + struct irq_domain *domain; + void __iomem *base; + struct irq_chip irqchip; + u8 gicoff; +}; + +static void msc313_intc_maskunmask(struct msc313_intc *intc, int hwirq, bool mask) +{ + int regoff = REGOFF(hwirq); + void __iomem *addr = intc->base + REGOFF_MASK + regoff; + u16 bit = IRQBIT(hwirq); + u16 reg = readw_relaxed(addr); + + if (mask) + reg |= bit; + else + reg &= ~bit; + + writew_relaxed(reg, addr); +} + +static void msc313_intc_mask_irq(struct irq_data *data) +{ + struct msc313_intc *intc = data->chip_data; + + msc313_intc_maskunmask(intc, data->hwirq, true); + irq_chip_mask_parent(data); +} + +static void msc313_intc_unmask_irq(struct irq_data *data) +{ + struct msc313_intc *intc = data->chip_data; + + msc313_intc_maskunmask(intc, data->hwirq, false); + irq_chip_unmask_parent(data); +} + +static int msc313_intc_set_type_irq(struct irq_data *data, unsigned int flow_type) +{ + struct msc313_intc *intc = data->chip_data; + int irq = data->hwirq; + int regoff = REGOFF(irq); + void __iomem *addr = intc->base + REGOFF_POLARITY + regoff; + u16 bit = IRQBIT(irq); + u16 reg = readw_relaxed(addr); + + if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH)) + reg &= ~bit; + else + reg |= bit; + + writew_relaxed(reg, addr); + return 0; +} + +static void msc313_intc_irq_eoi(struct irq_data *data) +{ + struct msc313_intc *intc = data->chip_data; + int irq = data->hwirq; + int regoff = REGOFF(irq); + void __iomem *addr = intc->base + REGOFF_STATUSCLEAR + regoff; + u16 bit = IRQBIT(irq); + u16 reg = readw_relaxed(addr); + + reg |= bit; + writew_relaxed(reg, addr); + irq_chip_eoi_parent(data); +} + +static int msc313_intc_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (!is_of_node(fwspec->fwnode) || fwspec->param_count != 2) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1]; + + return 0; +} + +static int msc313_intc_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + struct msc313_intc *intc = domain->host_data; + + if (fwspec->param_count != 2) + return -EINVAL; + + irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0], &intc->irqchip, intc); + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param[0] = GIC_SPI; + parent_fwspec.param[1] = fwspec->param[0] + intc->gicoff; + parent_fwspec.param[2] = fwspec->param[1]; + parent_fwspec.param_count = 3; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); +} + +static const struct irq_domain_ops msc313_intc_domain_ops = { + .translate = msc313_intc_domain_translate, + .alloc = msc313_intc_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int msc313_intc_of_init(struct device_node *node, + struct device_node *parent, + void (*eoi)(struct irq_data *data)) +{ + struct irq_domain *domain_parent; + struct msc313_intc *intc; + int ret = 0; + u32 gicoffset, numirqs; + + if (of_property_read_u32(node, "mstar,gic-offset", &gicoffset)) { + ret = -EINVAL; + goto out; + } + + if (of_property_read_u32(node, "mstar,nr-interrupts", &numirqs)) { + ret = -EINVAL; + goto out; + } + + domain_parent = irq_find_host(parent); + if (!domain_parent) { + ret = -EINVAL; + goto out; + } + + intc = kzalloc(sizeof(*intc), GFP_KERNEL); + if (!intc) { + ret = -ENOMEM; + goto out; + } + + intc->base = of_iomap(node, 0); + if (IS_ERR(intc->base)) { + ret = PTR_ERR(intc->base); + goto free_intc; + } + + intc->irqchip.name = node->name; + intc->irqchip.irq_mask = msc313_intc_mask_irq; + intc->irqchip.irq_unmask = msc313_intc_unmask_irq; + intc->irqchip.irq_eoi = eoi; + intc->irqchip.irq_set_type = msc313_intc_set_type_irq; + intc->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; + + intc->gicoff = gicoffset; + + intc->domain = irq_domain_add_hierarchy(domain_parent, 0, numirqs, node, + &msc313_intc_domain_ops, intc); + if (!intc->domain) { + ret = -ENOMEM; + goto unmap; + } + + return 0; + +unmap: + iounmap(intc->base); +free_intc: + kfree(intc); +out: + return ret; +} + +static int __init msc313_intc_irq_of_init(struct device_node *node, + struct device_node *parent) +{ + return msc313_intc_of_init(node, parent, irq_chip_eoi_parent); +}; + +static int __init msc313_intc_fiq_of_init(struct device_node *node, + struct device_node *parent) +{ + return msc313_intc_of_init(node, parent, msc313_intc_irq_eoi); +}; + +IRQCHIP_DECLARE(msc313_intc_irq, "mstar,msc313-intc-irq", + msc313_intc_irq_of_init); +IRQCHIP_DECLARE(mstar_intc_fiq, "mstar,msc313-intc-fiq", + msc313_intc_fiq_of_init); -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver 2020-08-05 11:00 ` [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver Daniel Palmer @ 2020-08-05 16:26 ` Marc Zyngier 2020-08-06 10:03 ` Daniel Palmer 0 siblings, 1 reply; 10+ messages in thread From: Marc Zyngier @ 2020-08-05 16:26 UTC (permalink / raw) To: Daniel Palmer Cc: devicetree, jason, arnd, linux-kernel, robh+dt, mark-pk.tsai, tglx, Willy Tarreau, linux-arm-kernel [+ Mark-PK Tsai] Hi Daniel, On 2020-08-05 12:00, Daniel Palmer wrote: > Add a driver for the two peripheral interrupt controllers > in MStar MSC313 and other MStar/Sigmastar Armv7 SoCs. > > Supports both the "IRQ" and "FIQ" controllers that > forward interrupts from the various IP blocks inside the > SoC to the ARM GIC. > > They are basically the same thing except for one difference: > The FIQ controller needs to clear the interrupt and the IRQ > controller doesn't. > > Signed-off-by: Daniel Palmer <daniel@0x0f.com> > Tested-by: Willy Tarreau <w@1wt.eu> > --- > MAINTAINERS | 1 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++++++++++++++ > 3 files changed, 212 insertions(+) > create mode 100644 drivers/irqchip/irq-msc313-intc.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 6e64d17aad7b..4d07403a7726 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -2157,6 +2157,7 @@ F: arch/arm/boot/dts/infinity*.dtsi > F: arch/arm/boot/dts/mercury*.dtsi > F: arch/arm/boot/dts/mstar-v7.dtsi > F: arch/arm/mach-mstar/ > +F: drivers/irqchip/irq-msc313-intc.c > > ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT > M: Michael Petchkovsky <mkpetch@internode.on.net> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index 133f9c45744a..67f3ae3507b8 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += > irq-loongson-htpic.o > obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o > obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o > obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o > +obj-$(CONFIG_ARCH_MSTARV7) += irq-msc313-intc.o > diff --git a/drivers/irqchip/irq-msc313-intc.c > b/drivers/irqchip/irq-msc313-intc.c > new file mode 100644 > index 000000000000..b50f5c858d38 > --- /dev/null > +++ b/drivers/irqchip/irq-msc313-intc.c > @@ -0,0 +1,210 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2019 Daniel Palmer > + */ > + > +#include <linux/irq.h> > +#include <linux/irqchip.h> > +#include <linux/irqdomain.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +#define REGOFF_MASK 0x0 > +#define REGOFF_POLARITY 0x10 > +#define REGOFF_STATUSCLEAR 0x20 > +#define IRQSPERREG 16 > +#define IRQBIT(hwirq) BIT((hwirq % IRQSPERREG)) > +#define REGOFF(hwirq) ((hwirq >> 4) * 4) > + > +struct msc313_intc { > + struct irq_domain *domain; > + void __iomem *base; > + struct irq_chip irqchip; Why do you need to embed the irq_chip on a per-controller basis? > + u8 gicoff; Given that basic SPIs can be in the 32-1019 range, this is at best risky. u32s are free, please use them. > +}; > + > +static void msc313_intc_maskunmask(struct msc313_intc *intc, int > hwirq, bool mask) > +{ > + int regoff = REGOFF(hwirq); > + void __iomem *addr = intc->base + REGOFF_MASK + regoff; > + u16 bit = IRQBIT(hwirq); > + u16 reg = readw_relaxed(addr); > + > + if (mask) > + reg |= bit; > + else > + reg &= ~bit; > + > + writew_relaxed(reg, addr); RMW on a shared MMIO register. Not going to end well. This is valid for all the callbacks, I believe. Also, please inline the maskunmask code in their respective callers. It will be much more readable. > +} > + > +static void msc313_intc_mask_irq(struct irq_data *data) > +{ > + struct msc313_intc *intc = data->chip_data; > + > + msc313_intc_maskunmask(intc, data->hwirq, true); > + irq_chip_mask_parent(data); > +} > + > +static void msc313_intc_unmask_irq(struct irq_data *data) > +{ > + struct msc313_intc *intc = data->chip_data; > + > + msc313_intc_maskunmask(intc, data->hwirq, false); > + irq_chip_unmask_parent(data); > +} > + > +static int msc313_intc_set_type_irq(struct irq_data *data, unsigned > int flow_type) > +{ > + struct msc313_intc *intc = data->chip_data; > + int irq = data->hwirq; > + int regoff = REGOFF(irq); > + void __iomem *addr = intc->base + REGOFF_POLARITY + regoff; > + u16 bit = IRQBIT(irq); > + u16 reg = readw_relaxed(addr); Please try to write this in a more readable way. For example: struct msc313_intc *intc = data->chip_data; void __iomem *addr; u16 reg, bit; addr = intc->base + REGOFF_POLARITY + REGOFF(d->hwirq); reg = readw_relaxed(addr); bit = IRQBIT(d->hwirq); White space is free, and some of the variables are really useless. > + > + if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH)) > + reg &= ~bit; > + else > + reg |= bit; I don't follow grasp the logic here. What happens on EDGE_BOTH, for example? > + > + writew_relaxed(reg, addr); Surely you need to communicate the change of signalling mode to the parent irqchip, don't you? > + return 0; > +} > + > +static void msc313_intc_irq_eoi(struct irq_data *data) > +{ > + struct msc313_intc *intc = data->chip_data; > + int irq = data->hwirq; > + int regoff = REGOFF(irq); > + void __iomem *addr = intc->base + REGOFF_STATUSCLEAR + regoff; > + u16 bit = IRQBIT(irq); > + u16 reg = readw_relaxed(addr); > + > + reg |= bit; > + writew_relaxed(reg, addr); > + irq_chip_eoi_parent(data); > +} > + > +static int msc313_intc_domain_translate(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + unsigned long *hwirq, > + unsigned int *type) > +{ > + if (!is_of_node(fwspec->fwnode) || fwspec->param_count != 2) > + return -EINVAL; > + > + *hwirq = fwspec->param[0]; Don't you want to check that the input you get is actually in range? Not a big deal, given that you then use it as an input parameter to the GIC driver, it'd better be correct. > + *type = fwspec->param[1]; > + > + return 0; > +} > + > +static int msc313_intc_domain_alloc(struct irq_domain *domain, > unsigned int virq, > + unsigned int nr_irqs, void *data) > +{ > + struct irq_fwspec *fwspec = data; > + struct irq_fwspec parent_fwspec; > + struct msc313_intc *intc = domain->host_data; > + > + if (fwspec->param_count != 2) > + return -EINVAL; > + > + irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0], > &intc->irqchip, intc); > + > + parent_fwspec.fwnode = domain->parent->fwnode; > + parent_fwspec.param[0] = GIC_SPI; > + parent_fwspec.param[1] = fwspec->param[0] + intc->gicoff; > + parent_fwspec.param[2] = fwspec->param[1]; > + parent_fwspec.param_count = 3; > + > + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, > + &parent_fwspec); > +} > + > +static const struct irq_domain_ops msc313_intc_domain_ops = { > + .translate = msc313_intc_domain_translate, > + .alloc = msc313_intc_domain_alloc, > + .free = irq_domain_free_irqs_common, > +}; > + > +static int msc313_intc_of_init(struct device_node *node, > + struct device_node *parent, > + void (*eoi)(struct irq_data *data)) > +{ > + struct irq_domain *domain_parent; > + struct msc313_intc *intc; > + int ret = 0; > + u32 gicoffset, numirqs; > + > + if (of_property_read_u32(node, "mstar,gic-offset", &gicoffset)) { > + ret = -EINVAL; > + goto out; > + } > + > + if (of_property_read_u32(node, "mstar,nr-interrupts", &numirqs)) { > + ret = -EINVAL; > + goto out; > + } > + > + domain_parent = irq_find_host(parent); > + if (!domain_parent) { > + ret = -EINVAL; > + goto out; > + } > + > + intc = kzalloc(sizeof(*intc), GFP_KERNEL); > + if (!intc) { > + ret = -ENOMEM; > + goto out; > + } > + > + intc->base = of_iomap(node, 0); > + if (IS_ERR(intc->base)) { > + ret = PTR_ERR(intc->base); > + goto free_intc; > + } > + > + intc->irqchip.name = node->name; No, please. /proc/interrupt isn't a dumping ground for DT related information. We have debugfs for that. > + intc->irqchip.irq_mask = msc313_intc_mask_irq; > + intc->irqchip.irq_unmask = msc313_intc_unmask_irq; > + intc->irqchip.irq_eoi = eoi; > + intc->irqchip.irq_set_type = msc313_intc_set_type_irq; > + intc->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; This needs to be a static irq_chip structure. Use two for the EOI weirdness, or test a flag in your eoi callback. > + > + intc->gicoff = gicoffset; > + > + intc->domain = irq_domain_add_hierarchy(domain_parent, 0, numirqs, > node, > + &msc313_intc_domain_ops, intc); > + if (!intc->domain) { > + ret = -ENOMEM; > + goto unmap; > + } > + > + return 0; > + > +unmap: > + iounmap(intc->base); > +free_intc: > + kfree(intc); > +out: > + return ret; > +} > + > +static int __init msc313_intc_irq_of_init(struct device_node *node, > + struct device_node *parent) > +{ > + return msc313_intc_of_init(node, parent, irq_chip_eoi_parent); > +}; > + > +static int __init msc313_intc_fiq_of_init(struct device_node *node, > + struct device_node *parent) > +{ > + return msc313_intc_of_init(node, parent, msc313_intc_irq_eoi); > +}; > + > +IRQCHIP_DECLARE(msc313_intc_irq, "mstar,msc313-intc-irq", > + msc313_intc_irq_of_init); > +IRQCHIP_DECLARE(mstar_intc_fiq, "mstar,msc313-intc-fiq", > + msc313_intc_fiq_of_init); This driver has a massive feeling of déja-vu. It is almost a copy of the one posted at [1], which I reviewed early this week. The issues are the exact same, and I'm 98% sure this is the same IP block used by two SoC vendors. Please talk to each other and come up with a single driver. Thanks, M. [1] https://lore.kernel.org/r/20200803062214.24076-1-mark-pk.tsai@mediatek.com -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver 2020-08-05 16:26 ` Marc Zyngier @ 2020-08-06 10:03 ` Daniel Palmer 2020-08-06 12:36 ` Marc Zyngier 0 siblings, 1 reply; 10+ messages in thread From: Daniel Palmer @ 2020-08-06 10:03 UTC (permalink / raw) To: Marc Zyngier Cc: DTML, jason, Arnd Bergmann, linux-kernel, Rob Herring, mark-pk.tsai, tglx, Willy Tarreau, linux-arm-kernel Hi Marc, On Thu, 6 Aug 2020 at 01:26, Marc Zyngier <maz@kernel.org> wrote: > > +struct msc313_intc { > > + struct irq_domain *domain; > > + void __iomem *base; > > + struct irq_chip irqchip; > > Why do you need to embed the irq_chip on a per-controller basis? Current chips have 1 instance of each type of controller but some of the newer ones seem to have an extra copy of the non-FIQ version with different offset to the GIC. > > +}; > > + > > +static void msc313_intc_maskunmask(struct msc313_intc *intc, int > > hwirq, bool mask) > > +{ > > + int regoff = REGOFF(hwirq); > > + void __iomem *addr = intc->base + REGOFF_MASK + regoff; > > + u16 bit = IRQBIT(hwirq); > > + u16 reg = readw_relaxed(addr); > > + > > + if (mask) > > + reg |= bit; > > + else > > + reg &= ~bit; > > + > > + writew_relaxed(reg, addr); > > RMW on a shared MMIO register. Not going to end well. This is valid > for all the callbacks, I believe. Do you have any suggestions on how to resolve that? It seems usually an interrupt controller has set and clear registers to get around this. Would defining a spinlock at the top of the driver and using that around the read and modify sequences be good enough? > > + > > + if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH)) > > + reg &= ~bit; > > + else > > + reg |= bit; > > I don't follow grasp the logic here. What happens on EDGE_BOTH, for > example? To be honest I don't quite remember. I'll check and rewrite this. > This driver has a massive feeling of déja-vu. It is almost > a copy of the one posted at [1], which I reviewed early > this week. The issues are the exact same, and I'm 98% > sure this is the same IP block used by two SoC vendors. This would make a lot of sense considering MediaTek bought MStar for their TV SoCs. The weirdness with only using 16 bits in a register suggests they've inherited the shared ARM/8051 bus that the MStar chips have. Thanks for the tip off. Cheers, Daniel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver 2020-08-06 10:03 ` Daniel Palmer @ 2020-08-06 12:36 ` Marc Zyngier 0 siblings, 0 replies; 10+ messages in thread From: Marc Zyngier @ 2020-08-06 12:36 UTC (permalink / raw) To: Daniel Palmer Cc: DTML, jason, Arnd Bergmann, linux-kernel, Rob Herring, mark-pk.tsai, tglx, Willy Tarreau, linux-arm-kernel On 2020-08-06 11:03, Daniel Palmer wrote: > Hi Marc, > > On Thu, 6 Aug 2020 at 01:26, Marc Zyngier <maz@kernel.org> wrote: >> > +struct msc313_intc { >> > + struct irq_domain *domain; >> > + void __iomem *base; >> > + struct irq_chip irqchip; >> >> Why do you need to embed the irq_chip on a per-controller basis? > > Current chips have 1 instance of each type of controller but some of > the > newer ones seem to have an extra copy of the non-FIQ version with > different > offset to the GIC. It is much better to have an irqchip structure per irqchip type, rather than one per instance, as you can then make the irqchip const. It also saves memory when you have more than a single instance. The only case where it doesn't work is when PM gets involved, as the parent_device pointer is stupidly stored in the irqchip device. > >> > +}; >> > + >> > +static void msc313_intc_maskunmask(struct msc313_intc *intc, int >> > hwirq, bool mask) >> > +{ >> > + int regoff = REGOFF(hwirq); >> > + void __iomem *addr = intc->base + REGOFF_MASK + regoff; >> > + u16 bit = IRQBIT(hwirq); >> > + u16 reg = readw_relaxed(addr); >> > + >> > + if (mask) >> > + reg |= bit; >> > + else >> > + reg &= ~bit; >> > + >> > + writew_relaxed(reg, addr); >> >> RMW on a shared MMIO register. Not going to end well. This is valid >> for all the callbacks, I believe. > > Do you have any suggestions on how to resolve that? It seems usually > an interrupt controller has set and clear registers to get around this. > Would defining a spinlock at the top of the driver and using that > around > the read and modify sequences be good enough? Yes, a spinlock is the conventional way to solve it. Make sure you use the irqsave/irqrestore versions, as mask/unmask can also occur whilst in interrupt context. > >> > + >> > + if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH)) >> > + reg &= ~bit; >> > + else >> > + reg |= bit; >> >> I don't follow grasp the logic here. What happens on EDGE_BOTH, for >> example? > > To be honest I don't quite remember. I'll check and rewrite this. > >> This driver has a massive feeling of déja-vu. It is almost >> a copy of the one posted at [1], which I reviewed early >> this week. The issues are the exact same, and I'm 98% >> sure this is the same IP block used by two SoC vendors. > > This would make a lot of sense considering MediaTek bought MStar > for their TV SoCs. The weirdness with only using 16 bits in a register > suggests they've inherited the shared ARM/8051 bus that the MStar > chips have. Thanks for the tip off. It is indeed the 16bit accesses that reminded me of the MTK code, as that's very unusual. Hopefully you can work with the MTK guys to resolve this quickly. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi 2020-08-05 11:00 [PATCH 0/3] irqchip: mstar: msc313 intc driver Daniel Palmer 2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer 2020-08-05 11:00 ` [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver Daniel Palmer @ 2020-08-05 11:00 ` Daniel Palmer 2 siblings, 0 replies; 10+ messages in thread From: Daniel Palmer @ 2020-08-05 11:00 UTC (permalink / raw) To: linux-arm-kernel Cc: devicetree, jason, arnd, maz, Daniel Palmer, linux-kernel, robh+dt, tglx, Willy Tarreau Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7 dtsi. All of the known SoCs have both and at the same place with their common IPs using the same interrupt lines. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Tested-by: Willy Tarreau <w@1wt.eu> --- arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..2b3bb0886d1a 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,26 @@ reboot { mask = <0x79>; }; + intc_fiq: intc@201310 { + compatible = "mstar,msc313-intc-fiq"; + interrupt-controller; + reg = <0x201310 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <96>; + mstar,nr-interrupts = <32>; + }; + + intc_irq: intc@201350 { + compatible = "mstar,msc313-intc-irq"; + interrupt-controller; + reg = <0x201350 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <32>; + mstar,nr-interrupts = <64>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-08-06 14:47 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-08-05 11:00 [PATCH 0/3] irqchip: mstar: msc313 intc driver Daniel Palmer 2020-08-05 11:00 ` [PATCH 1/3] dt: bindings: interrupt-controller: Add binding description for msc313-intc Daniel Palmer 2020-08-06 14:10 ` Rob Herring 2020-08-06 14:15 ` Rob Herring 2020-08-06 14:46 ` Daniel Palmer 2020-08-05 11:00 ` [PATCH 2/3] irqchip: mstar: msc313-intc interrupt controller driver Daniel Palmer 2020-08-05 16:26 ` Marc Zyngier 2020-08-06 10:03 ` Daniel Palmer 2020-08-06 12:36 ` Marc Zyngier 2020-08-05 11:00 ` [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Daniel Palmer
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