From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE88EC25B74 for ; Fri, 24 May 2024 15:03:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NNswrbjP1gFZtdflawKFhWRCyhX/5fgUSHze77LW+GE=; b=uRmj88na/1UIk8 YmGYaA9mNjIzykGqgt5Nqgc2xLRniOzKB62Xu2RlEMFgF8t+IVJoEjuIc+q8THX+ChQ++rAVHZcYX JCLweehTFUA+b89ioRn/ORMFWfpWFSlz7J5RtSkkInn2npUQmjzynpS3c0JzJQJpMv6vltOTQppJ+ exQZl9pe2pokugr/r7Vk7uej1oLxp+obSaIeKdf62Bi9DECSHA4V4FmPDTBuRV05HfZ9CzR2Iw3eQ 08WkCZclOkr8hJ86UW6LF2gBQAvlHdC/PK6G4ukwHKWaFVrX+WtLdRxcP+cLi1qkmtQH5cnrD9y61 GrXhii81aIivl0i52JyQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sAWRt-00000009BG7-1vRm; Fri, 24 May 2024 15:03:13 +0000 Received: from out-171.mta0.migadu.com ([91.218.175.171]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sAWRq-00000009BFi-378v for linux-arm-kernel@lists.infradead.org; Fri, 24 May 2024 15:03:12 +0000 X-Envelope-To: dan.carpenter@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1716562986; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t9bLVr+GkFcIRkLEE2xi6Gq4uQdgtVR2m96QalOewfs=; b=f8qgCiBFT0iKngbIh5yIVDsyEoWOcyhplL8DknaJjzEX7VyBJJGzwU+rjsKXIvx5V6tqZ/ mvzSvjZRBUad4tbniOCyKf9A3iSo49GZ1l1e9wvqCLucL1uvlpS/8W7wpQoZiR6Yoqwxgn C2DMzuJ40deEHhdzGzxEAmH7xA8I5CA= X-Envelope-To: helgaas@kernel.org X-Envelope-To: lpieralisi@kernel.org X-Envelope-To: kw@linux.com X-Envelope-To: robh@kernel.org X-Envelope-To: linux-pci@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: thippeswamy.havalige@amd.com X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: bhelgaas@google.com X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: stable@vger.kernel.org X-Envelope-To: bharatku@xilinx.com Message-ID: <3e7a23ae-6423-4455-9ffb-4820ee2dc92d@linux.dev> Date: Fri, 24 May 2024 11:03:01 -0400 MIME-Version: 1.0 Subject: Re: [PATCH v3 2/7] PCI: xilinx-nwl: Fix off-by-one in IRQ handler To: Dan Carpenter Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org, Michal Simek , Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, Bjorn Helgaas , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Bharat Kumar Gogada References: <20240522222834.GA101664@bhelgaas> <9299ee92-a32b-4b82-aa37-c7087a5c1376@linux.dev> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_080310_951519_E9AF393F X-CRM114-Status: GOOD ( 16.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/24/24 10:56, Dan Carpenter wrote: > On Thu, May 23, 2024 at 11:21:52AM -0400, Sean Anderson wrote: >> On 5/22/24 18:28, Bjorn Helgaas wrote: >> > On Mon, May 20, 2024 at 10:53:57AM -0400, Sean Anderson wrote: >> >> MSGF_LEG_MASK is laid out with INTA in bit 0, INTB in bit 1, INTC in bit >> >> 2, and INTD in bit 3. Hardware IRQ numbers start at 0, and we register >> >> PCI_NUM_INTX irqs. So to enable INTA (aka hwirq 0) we should set bit 0. >> >> Remove the subtraction of one. This fixes the following UBSAN error: >> > >> > Thanks for these details! >> > >> > I guess UBSAN == "undefined behavior sanitizer", right? That sounds >> > like an easy way to find this but not the way users are likely to find >> > it. >> >> It's pretty likely they will find it this way, since I found it this way >> and no one else had ;) >> >> > I assume users would notice spurious and missing interrupts, e.g., >> > a driver that tried to enable INTB would have actually enabled INTA, >> > so we'd see spurious INTA interrupts and the driver would never see >> > the INTB it expected. >> > >> > And a driver that tried to enable INTA would never see that interrupt, >> > and we might not set any bit in MSGF_LEG_MASK? >> >> And yes, this would manifest as INTx interrupts being broken. >> > > It's so weird that it's been broken for seven years and no one reported > it. :/ If I had to guess it's because most PCIe hardware uses MSIs. Unless you plugged in a PCI bridge there's almost no reason to use INTx at all. --Sean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel